公开(公告)号：WO2021112955A8

公开(公告)日：2021-06-10

申请号：PCT/US2020/055198

申请日：2020-10-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： VANKAYALA, Vijayakrishna J.

IPC: G11C7/22 ,  G11C5/04 ,  G11C8/18 ,  G06F3/06 ,  G11C8/12 ,  G11C11/408 ,  G11C2207/2281 ,  G11C2207/229 ,  G11C5/066 ,  G11C7/065 ,  G11C7/1015 ,  G11C7/1063 ,  G11C7/1072 ,  G11C7/222

Abstract: Methods of operating a memory device are disclosed. A method may include receiving, at a first die of a number of dies, a first number of bits including one or more command bits, one or more identification bits, and a first number of address bits associated with a command during a first clock cycle. The method may further include conveying, from the first die to at least one other die, at least some of the first number of bits. Further, the method may include receiving, at the first die, a second number of bits including a second number of address bits associated with the command during a second, subsequent clock cycle. Also, the method may include conveying, from the first die to the at least one other die, at least some of the second number of bits. Memory devices and electronic systems are also disclosed.

公开(公告)号：WO2022005820A1

公开(公告)日：2022-01-06

申请号：PCT/US2021/038507

申请日：2021-06-22

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MATSUBARA, Yasushi ,  JONO, Yusuke ,  MORGAN, Donald, Martin ,  YAMAMOTO, Nobuo

IPC: G11C11/22 ,  G11C7/06 ,  G11C11/2273 ,  G11C11/2275 ,  G11C2207/2281 ,  G11C2207/229 ,  G11C7/065 ,  G11C7/1027 ,  G11C7/1039 ,  G11C7/18 ,  G11C7/20

Abstract: Methods, systems, and devices for system and method for reading and writing memory management data through a non-volatile cell based register are described. A memory device may include a set of latch units addressable via a set of row lines and a set of column lines. Each latch unit may include a sense amplifier coupled with a first line and a first non-volatile capacitor coupled with the first line and a second line, where the first capacitor is configured to store a charge representing one or more bits. Additionally, each latch unit may include a second capacitor coupled with the first line and a third line, where the second capacitor is configured to amplify a voltage at the first line based on the charge stored in the first capacitor.