公开(公告)号：WO2022005820A1

公开(公告)日：2022-01-06

申请号：PCT/US2021/038507

申请日：2021-06-22

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MATSUBARA, Yasushi ,  JONO, Yusuke ,  MORGAN, Donald, Martin ,  YAMAMOTO, Nobuo

IPC: G11C11/22 ,  G11C7/06 ,  G11C11/2273 ,  G11C11/2275 ,  G11C2207/2281 ,  G11C2207/229 ,  G11C7/065 ,  G11C7/1027 ,  G11C7/1039 ,  G11C7/18 ,  G11C7/20

Abstract: Methods, systems, and devices for system and method for reading and writing memory management data through a non-volatile cell based register are described. A memory device may include a set of latch units addressable via a set of row lines and a set of column lines. Each latch unit may include a sense amplifier coupled with a first line and a first non-volatile capacitor coupled with the first line and a second line, where the first capacitor is configured to store a charge representing one or more bits. Additionally, each latch unit may include a second capacitor coupled with the first line and a third line, where the second capacitor is configured to amplify a voltage at the first line based on the charge stored in the first capacitor.

公开(公告)号：WO2022031349A1

公开(公告)日：2022-02-10

申请号：PCT/US2021/034643

申请日：2021-05-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： CUI, Zhixin ,  CHIBVONGODZE, Hardwell ,  GAUTAM, Rajdeep

IPC: G11C16/10 ,  G11C11/22 ,  G11C16/04 ,  G11C16/26 ,  G11C17/16 ,  G11C17/18 ,  H01L23/522 ,  G11C11/005 ,  G11C11/223 ,  G11C11/2273 ,  G11C11/2275 ,  G11C16/0408 ,  G11C16/0466 ,  G11C2216/26 ,  H01L23/5226 ,  H01L27/11206 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11582 ,  H01L27/11587 ,  H01L27/1159 ,  H01L27/11597

Abstract: First alternating stacks of first insulating strips and first spacer material strips is formed in a first device region, second alternating stacks of second insulating strips and second spacer material strips are formed in a second device region. Each of the first line trenches is filled with a respective laterally alternating sequence of memory stack structures and first dielectric pillar structures to form a three-dimensional NAND memory. Each of the memory stack structures includes a vertical semiconductor channel and a vertical stack of memory elements. Each of the second line trenches with a respective laterally alternating sequence of active region assemblies of lateral field effect transistors and second dielectric pillar structures to form a three-dimensional NOR memory. Each of the active region assemblies includes a source pillar, a drain pillar, and a tubular channel region. The spacer material strips include, or are subsequently replaced with, electrically conductive strips.

公开(公告)号：WO2022000486A1

公开(公告)日：2022-01-06

申请号：PCT/CN2020/100210

申请日：2020-07-03

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： TANG, Qiang

IPC: G11C11/22 ,  G11C11/221 ,  G11C11/223 ,  G11C11/225 ,  G11C11/2255 ,  G11C11/2257 ,  G11C11/2259 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/40 ,  G11C2213/71 ,  G11C5/02 ,  H01L27/11587 ,  H01L27/1159 ,  H01L27/11597

Abstract: A programming method for a three-dimensional ferroelectric memory device is disclosed. The programming method includes applying a first voltage on a selected word line of a target memory cell. The target memory cell has a first logic state and a second logic state corresponding to a first threshold voltage and a second threshold voltage, respectively. The first and second threshold voltages are determined by two opposite electric polarization directions of a ferroelectric film in the target memory cell. The programming method also includes applying a second voltage on a selected bit line, where a voltage difference between the first and second voltages has a magnitude larger than a coercive voltage of the ferroelectric film such that the target memory cell is switched from the first logic state to the second logic state.

公开(公告)号：WO2021126558A2

公开(公告)日：2021-06-24

申请号：PCT/US2020/063415

申请日：2020-12-04

Applicant: MICRON TECHNOLOGY, INC.

Inventor： SWAMI, Shivam ,  EILERT, Sean, S. ,  AKEL, Ameen, D.

IPC: H01L27/24 ,  H01L45/00 ,  G11C11/221 ,  G11C11/2255 ,  G11C11/2257 ,  G11C11/2259 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/2293 ,  G11C11/2297

Abstract: Methods, systems, and devices for via formation in a memory device are described. A memory cell stack for a memory array may be formed. In some examples, the memory cell stack may comprise a storage element. A via may also be formed in an area outside of the memory array, and the via may protrude from a material that surrounds the via. A material may then be formed above the memory cell stack and also above the via, and the top surface of the barrier material may be planarized until at least a portion of the via is exposed. A subsequently formed material may thereby be in direct contact with the top of the via, while a portion of the initially formed material may remain above the memory cell stack.

公开(公告)号：WO2021126557A1

公开(公告)日：2021-06-24

申请号：PCT/US2020/063414

申请日：2020-12-04

Applicant: MICRON TECHNOLOGY, INC.

Inventor： SWAMI, Shivam ,  EILERT, Sean, S. ,  AKEL, Ameen, D.

IPC: G11C11/22 ,  G11C7/06 ,  G06F3/06 ,  G11C11/221 ,  G11C11/2255 ,  G11C11/2257 ,  G11C11/2259 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/2297

Abstract: Methods, systems, and devices for memory accessing with auto-precharge are described. For example, a memory system may be configured to support an activate with auto-precharge command, which may be associated with a memory device opening a page of memory cells, latching respective logic states stored by the memory cells at a row buffer, writing logic states back to the page of memory cells, and maintaining the latched logic states at the row buffer (e.g., while maintaining power to latches of the row buffer, after closing the page of memory cells, while the page of memory cells is closed).

公开(公告)号：WO2021194996A1

公开(公告)日：2021-09-30

申请号：PCT/US2021/023535

申请日：2021-03-22

Applicant: HSU, Fu-Chang

Inventor： HSU, Fu-Chang

IPC: H01L27/11551 ,  H01L27/11553 ,  H01L27/11563 ,  H01L27/11578 ,  H01L27/1158 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/2273 ,  G11C11/2275 ,  G11C13/004 ,  G11C13/0069 ,  G11C16/10 ,  G11C16/26 ,  G11C17/18 ,  G11C2213/71 ,  G11C2213/75 ,  H01L27/11206 ,  H01L27/11582 ,  H01L27/11597 ,  H01L27/228 ,  H01L27/2454 ,  H01L27/249

Abstract: A three dimensional double-density memory array is disclosed. In an embodiment, a three-dimensional (3D) double density array comprises a string of memory devices that are configured so that a first portion of the memory devices form a first channel and a second portion of the memory devices form a second channel. The array also comprises a plurality of word lines coupled to the string of memory devices. Each word line is coupled to a memory device that forms the first channel and a memory device that forms the second channel. The array also comprises at least one drain select gate that couples the first and second channels to a bit line.

公开(公告)号：WO2021194833A1

公开(公告)日：2021-09-30

申请号：PCT/US2021/022895

申请日：2021-03-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： VISCONTI, Angelo ,  PAZZOCCO, Riccardo ,  STRAND, Jonathan, J. ,  MAJERUS, Kevin, T.

IPC: G11C11/22 ,  G11C5/14 ,  G11C11/221 ,  G11C11/2259 ,  G11C11/2273 ,  G11C11/2275 ,  G11C29/50

Abstract: Methods, systems, and devices for charge leakage detection for memory system reliability are described. In accordance with examples as disclosed herein, a memory system may employ memory management techniques configured to identify precursors of charge leakage in a memory device, and take preventative action based on such identified precursors. For example, a memory system may be configured to perform a leakage detection evaluation for a memory array, which may include various biasing and evaluation operations to identify whether a leakage condition of the memory array may affect operational reliability. Based on such an evaluation, the memory device, or a host device in communication with the memory device, may take various preventative measures to avoid operational failures of the memory device or host device that may result from ongoing operation of a memory array associated with charge leakage, thereby improving reliability of the memory system.