公开(公告)号：WO2021252163A1

公开(公告)日：2021-12-16

申请号：PCT/US2021/033457

申请日：2021-05-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： YAMAMOTO, Nobuo ,  MORGAN, Donald, Martin ,  WONG, Victor ,  KWAK, Jongtae

IPC: G11C11/22 ,  G06F11/10 ,  G11C11/221 ,  G11C11/401 ,  G11C16/10 ,  G11C16/26 ,  G11C29/20 ,  G11C29/42 ,  G11C29/44

Abstract: Methods, systems, and devices for error control for memory device are described. A memory device may be configured to perform memory management operations including error control operations. For example, a memory device may be configured to perform an error control operation on data stored in a first memory cell coupled with a source row of a memory array. The memory device may be configured to write the data to a second memory cell coupled with the target row of the memory array based on performing the error control operation on the data and determine whether the management operation is complete based at least in part on the first column address of the first memory cell. The memory device may also generate an output signal to perform the error control operation on a third memory cell coupled with the source row based on determining whether the management operation is complete.

公开(公告)号：WO2022005820A1

公开(公告)日：2022-01-06

申请号：PCT/US2021/038507

申请日：2021-06-22

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MATSUBARA, Yasushi ,  JONO, Yusuke ,  MORGAN, Donald, Martin ,  YAMAMOTO, Nobuo

IPC: G11C11/22 ,  G11C7/06 ,  G11C11/2273 ,  G11C11/2275 ,  G11C2207/2281 ,  G11C2207/229 ,  G11C7/065 ,  G11C7/1027 ,  G11C7/1039 ,  G11C7/18 ,  G11C7/20

Abstract: Methods, systems, and devices for system and method for reading and writing memory management data through a non-volatile cell based register are described. A memory device may include a set of latch units addressable via a set of row lines and a set of column lines. Each latch unit may include a sense amplifier coupled with a first line and a first non-volatile capacitor coupled with the first line and a second line, where the first capacitor is configured to store a charge representing one or more bits. Additionally, each latch unit may include a second capacitor coupled with the first line and a third line, where the second capacitor is configured to amplify a voltage at the first line based on the charge stored in the first capacitor.