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    MEMORY ARRAY WITH MULTIPLEXED SELECT LINES
    4.
    发明申请
    MEMORY ARRAY WITH MULTIPLEXED SELECT LINES 审中-公开

    公开(公告)号：WO2021194834A1

    公开(公告)日：2021-09-30

    申请号：PCT/US2021/022897

    申请日：2021-03-18

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： VIMERCATI, Daniele

    IPC: G11C11/22 ,  G11C11/221 ,  G11C11/2259 ,  G11C11/2273

    Abstract: Methods, systems, and devices for memory array with multiplexed select lines are described. In some cases, a memory cell of the memory device may include a storage component, a first transistor coupled with a word line, and a second transistor coupled with a first select line to selectively couple the memory cell with a first digit line. A third transistor may be coupled with the first digit line and a sense component common to a set of digit lines and a set of select lines. A second select line may be coupled with the third transistor and configured to couple the sense component with the first digit line and to couple the sense component with a second digit line. The sense component may determine a logic state stored by the memory cell based on the signal from the first digit line and the signal from the second digit line.

    CHARGE LEAKAGE DETECTION FOR MEMORY SYSTEM RELIABILITY
    5.
    发明申请
    CHARGE LEAKAGE DETECTION FOR MEMORY SYSTEM RELIABILITY 审中-公开

    公开(公告)号：WO2021194833A1

    公开(公告)日：2021-09-30

    申请号：PCT/US2021/022895

    申请日：2021-03-18

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： VISCONTI, Angelo ,  PAZZOCCO, Riccardo ,  STRAND, Jonathan, J. ,  MAJERUS, Kevin, T.

    IPC: G11C11/22 ,  G11C5/14 ,  G11C11/221 ,  G11C11/2259 ,  G11C11/2273 ,  G11C11/2275 ,  G11C29/50

    Abstract: Methods, systems, and devices for charge leakage detection for memory system reliability are described. In accordance with examples as disclosed herein, a memory system may employ memory management techniques configured to identify precursors of charge leakage in a memory device, and take preventative action based on such identified precursors. For example, a memory system may be configured to perform a leakage detection evaluation for a memory array, which may include various biasing and evaluation operations to identify whether a leakage condition of the memory array may affect operational reliability. Based on such an evaluation, the memory device, or a host device in communication with the memory device, may take various preventative measures to avoid operational failures of the memory device or host device that may result from ongoing operation of a memory array associated with charge leakage, thereby improving reliability of the memory system.

    MEMORY CELL BIASING TECHNIQUES DURING A READ OPERATION
    7.
    发明申请
    MEMORY CELL BIASING TECHNIQUES DURING A READ OPERATION 审中-公开

    公开(公告)号：WO2021202064A1

    公开(公告)日：2021-10-07

    申请号：PCT/US2021/021508

    申请日：2021-03-09

    Applicant: MICRON TECHNOLOGIES, INC.

    Inventor： LOCATELLI, Andrea ,  SERVALLI, Giorgio ,  VISCONTI, Angelo

    IPC: G11C11/22 ,  G11C11/221 ,  G11C11/2273 ,  G11C11/406 ,  G11C11/4091 ,  G11C11/4096 ,  G11C11/4097

    Abstract: Methods, systems, and devices for biasing a memory cell during a read operation are described. For example, a memory device may bias a memory cell to a first voltage (e.g., a read voltage) during an activation phase of a read operation. After biasing the memory cell to the first voltage, the memory device may bias the memory cell to a second voltage greater than the first voltage (e.g., a write voltage) during the activation phase of the read operation. After biasing the memory cell to the second voltage, the memory device may initiate a refresh phase of the read operation. Based on a value stored by the memory cell prior to biasing the memory cell to the first voltage, the memory device may initiate a precharge phase of the read operation.

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