公开(公告)号：WO2022268417A1

公开(公告)日：2022-12-29

申请号：PCT/EP2022/063663

申请日：2022-05-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  IBM UNITED KINGDOM LIMITED

Inventor： MIGNOT, Yann ,  PARK, Chanro ,  CHEN, Hsueh-Chung

IPC: H01L21/768 ,  H01L23/528 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76883 ,  H01L21/76892 ,  H01L23/5329

Abstract: A top cap layer covering a first metal line and a second metal line, horizontally between the first metal line and the second metal line is, in sequential order, a post cap liner, an air gap and the post cap liner. A first set of metal lines embedded in an upper surface of a dielectric, a second set of metal lines embedded below the dielectric and above the electronic components, a post cap liner covering the first set of metal lines, a cavity which dissects a first metal line of the first set of metal lines and extends to a second metal line of the second set of metal lines and dissects the second set of metal lines. Forming a cavity in a first metal line embedded in an upper surface of a dielectric, where the first metal line and the dielectric are covered by a top cap layer.

公开(公告)号：WO2023278387A1

公开(公告)日：2023-01-05

申请号：PCT/US2022/035235

申请日：2022-06-28

Applicant: APPLIED MATERIALS, INC.

Inventor： PARIKH, Suketu ,  JANSEN, Alexander ,  LEE, Joung Joo ,  LIU, Lequn

IPC: H01L21/768 ,  H01L21/67167 ,  H01L21/67184 ,  H01L21/67207 ,  H01L21/76807 ,  H01L21/7684 ,  H01L21/76846 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53238

Abstract: Interconnect structures on a substrate have low resistivity and high dopant interfaces. In some embodiments, the structures may have an opening with a sidewall from an upper surface to an underlying metallic layer of copper, a barrier layer of tantalum nitride formed on the sidewall of the opening, a liner layer of cobalt or ruthenium formed on the barrier layer and on the underlying metallic layer, a first copper layer with a dopant with a first dopant content formed on the liner layer and filling a lower portion of the opening to form a via - the first dopant content is approximately 0.5 percent to approximately 10 percent, and a second copper layer with the dopant with a second dopant content formed on the first copper layer and filling the at least one opening - the second dopant content is more than zero to approximately 0.5 percent of the dopant and is less than the first dopant content.

公开(公告)号：WO2023278384A1

公开(公告)日：2023-01-05

申请号：PCT/US2022/035231

申请日：2022-06-28

Applicant: APPLIED MATERIALS, INC.

Inventor： PARIKH, Suketu ,  JANSEN, Alexander ,  LEE, Joung Joo ,  LIU, Lequn

IPC: H01L21/768 ,  H01L21/285 ,  H01L21/02063 ,  H01L21/31053 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/7684 ,  H01L21/76846 ,  H01L21/76882 ,  H01L23/53238

Abstract: Methods for forming interconnects on a substrate with low resistivity and high dopant interfaces. In some embodiments, a method includes depositing a first copper layer with a dopant with a first dopant content of 0.5 percent to 10 percent in the interconnect by sputtering a first copper-based target at a first temperature of zero degrees Celsius to 200 degrees Celsius, annealing the substrate at a second temperature of 200 degrees Celsius to 400 degrees Celsius to reflow the first copper layer, depositing a second copper layer with the dopant with a second dopant content of zero percent to 0.5 percent by sputtering a second copper-based target at the first temperature of zero degrees Celsius to 200 degrees Celsius, and annealing the substrate at a third temperature of 200 degrees Celsius to 400 degrees Celsius to reflow the second copper layer.