公开(公告)号：WO2022268668A1

公开(公告)日：2022-12-29

申请号：PCT/EP2022/066652

申请日：2022-06-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  IBM DEUTSCHLAND GMBH

Inventor： LANZILLO, Nicholas ,  SHOBHA, Hosadurga ,  HUANG, Huai ,  CLEVENGER, Lawrence

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/532 ,  H01L23/535 ,  H01L23/522 ,  H01L23/48 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76883 ,  H01L21/76885 ,  H01L23/481 ,  H01L23/5222 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/5286 ,  H01L23/53209

Abstract: A semiconductor structure with one or more backside metal layers that include a plurality of portions of a floating metal layer separated by dielectric material from one or more power and ground lines in the backside metal layer. The height of each of the plurality of portions of the floating metal layer in each of the one or more backside metal layers and the distance between adjacent portions of the plurality of portions of the floating metal layer in each of the one or more backside metal layer correlates to the capacitance of each of the one or more backside metal layers.

公开(公告)号：WO2022237044A1

公开(公告)日：2022-11-17

申请号：PCT/CN2021/120247

申请日：2021-09-24

Applicant: 长鑫存储技术有限公司

Inventor： 吴双双 ,  李宗翰

IPC: H01L21/768 ,  H01L21/7684 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/485

Abstract: 本申请涉及一种半导体结构的制备方法，包括：提供基底；于所述基底内形成硅通孔，所述硅通孔的深度小于所述基底的厚度；于所述硅通孔的侧壁及底部形成内衬层，并于所述硅通孔内形成导电层；所述内衬层包括研磨停止层。

公开(公告)号：WO2021248426A1

公开(公告)日：2021-12-16

申请号：PCT/CN2020/095714

申请日：2020-06-12

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： HAN, Yuhui ,  ZHOU, Wenxi ,  XIA, Zhiliang ,  ZHAO, Lichuan

IPC: H01L27/1157 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  G11C16/04 ,  G11C16/34 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/535 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11578

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a memory stack and a plurality of memory strings. The memory stack includes interleaved conductive layers and dielectric layers. Each memory string extends vertically through the memory stack. The plurality of memory strings are divided into a plurality of regions of the memory stack in a plan view. The conductive layers include one or more drain select gate (DSG) lines configured to control drains of the plurality of memory strings. The numbers of the DSG lines are different among the plurality of regions. Each of the plurality of memory strings has a nominally same height.

公开(公告)号：WO2021146827A1

公开(公告)日：2021-07-29

申请号：PCT/CN2020/073107

申请日：2020-01-20

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： WU, Jianzhong ,  ZHANG, Kun ,  ZHAO, Tingting ,  SU, Rui ,  SUN, Zhongwang ,  ZHOU, Wenxi ,  XIA, Zhiliang

IPC: H01L27/1157 ,  H01L23/538 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/7684 ,  H01L21/76895 ,  H01L2221/1063 ,  H01L23/535 ,  H01L27/115 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11582

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack, a channel structure, a channel local contact, and a slit structure. The memory stack includes interleaved conductive layers and dielectric layers above the substrate. The channel structure extends vertically through the memory stack. The channel local contact is above and in contact with the channel structure. The slit structure extends vertically through the memory stack. The slit structure includes a contact including a first contact portion and a second contact portion above the first contact portion and having a different material of the first contact portion. An upper end of the second contact portion of the slit structure is flush with an upper end of the channel local contact.

公开(公告)号：WO2023278387A1

公开(公告)日：2023-01-05

申请号：PCT/US2022/035235

申请日：2022-06-28

Applicant: APPLIED MATERIALS, INC.

Inventor： PARIKH, Suketu ,  JANSEN, Alexander ,  LEE, Joung Joo ,  LIU, Lequn

IPC: H01L21/768 ,  H01L21/67167 ,  H01L21/67184 ,  H01L21/67207 ,  H01L21/76807 ,  H01L21/7684 ,  H01L21/76846 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53238

Abstract: Interconnect structures on a substrate have low resistivity and high dopant interfaces. In some embodiments, the structures may have an opening with a sidewall from an upper surface to an underlying metallic layer of copper, a barrier layer of tantalum nitride formed on the sidewall of the opening, a liner layer of cobalt or ruthenium formed on the barrier layer and on the underlying metallic layer, a first copper layer with a dopant with a first dopant content formed on the liner layer and filling a lower portion of the opening to form a via - the first dopant content is approximately 0.5 percent to approximately 10 percent, and a second copper layer with the dopant with a second dopant content formed on the first copper layer and filling the at least one opening - the second dopant content is more than zero to approximately 0.5 percent of the dopant and is less than the first dopant content.

公开(公告)号：WO2023278384A1

公开(公告)日：2023-01-05

申请号：PCT/US2022/035231

申请日：2022-06-28

Applicant: APPLIED MATERIALS, INC.

Inventor： PARIKH, Suketu ,  JANSEN, Alexander ,  LEE, Joung Joo ,  LIU, Lequn

IPC: H01L21/768 ,  H01L21/285 ,  H01L21/02063 ,  H01L21/31053 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/7684 ,  H01L21/76846 ,  H01L21/76882 ,  H01L23/53238

Abstract: Methods for forming interconnects on a substrate with low resistivity and high dopant interfaces. In some embodiments, a method includes depositing a first copper layer with a dopant with a first dopant content of 0.5 percent to 10 percent in the interconnect by sputtering a first copper-based target at a first temperature of zero degrees Celsius to 200 degrees Celsius, annealing the substrate at a second temperature of 200 degrees Celsius to 400 degrees Celsius to reflow the first copper layer, depositing a second copper layer with the dopant with a second dopant content of zero percent to 0.5 percent by sputtering a second copper-based target at the first temperature of zero degrees Celsius to 200 degrees Celsius, and annealing the substrate at a third temperature of 200 degrees Celsius to 400 degrees Celsius to reflow the second copper layer.