公开(公告)号：WO2023282955A1

公开(公告)日：2023-01-12

申请号：PCT/US2022/024726

申请日：2022-04-14

Applicant: APPLIED MATERIALS, INC.

Inventor： PARIKH, Suketu ,  BALSEANU, Mihaela A. ,  BHUYAN, Bhaskar Jyoti ,  LI, Ning ,  SALY, Mark Joseph ,  DANGERFIELD, Aaron Michael ,  THOMPSON, David ,  MALLICK, Abhijit B.

IPC: H01L21/768 ,  H01L21/32 ,  H01L21/02 ,  H01L21/67

Abstract: Methods and apparatus for processing a substrate are provided herein. For example, a method of processing a substrate comprises a) removing oxide from a metal layer disposed in a dielectric layer on the substrate disposed in a processing chamber, b) selectively depositing a self-assembled monolayer (SAM) on the metal layer using atomic layer deposition, c) depositing a precursor while supplying water to form one of an aluminum oxide (AlO) layer on the dielectric layer or a low-k dielectric layer on the dielectric layer, d) supplying at least one of hydrogen (H2) or ammonia (NH3) to remove the self-assembled monolayer (SAM), and e) depositing one of a silicon oxycarbonitride (SiOCN) layer or a silicon nitride (SiN) layer atop the metal layer and the one of the aluminum oxide (AlO) layer on the dielectric layer or the low-k dielectric layer on the dielectric layer.

公开(公告)号：WO2020056079A1

公开(公告)日：2020-03-19

申请号：PCT/US2019/050732

申请日：2019-09-12

Applicant: APPLIED MATERIALS, INC.

Inventor： PARIKH, Suketu

IPC: H01L21/768 ,  H01L21/311

Abstract: Processing methods may be performed to produce three-dimensional interconnects on a substrate. The methods may include forming a first metal interconnect layer over a semiconductor substrate. The methods may include forming a first dielectric layer over the first metal interconnect layer. The methods may include forming a second metal interconnect layer over the first dielectric layer. The methods may include forming a patterning mask overlying the second metal interconnect layer. The methods may also include simultaneously etching each of the first metal interconnect layer, the first dielectric layer, and the second metal interconnect layer to expose the substrate to produce a multilayer interconnect structure in a first lateral direction.

公开(公告)号：WO2023015116A1

公开(公告)日：2023-02-09

申请号：PCT/US2022/074149

申请日：2022-07-26

Applicant: APPLIED MATERIALS, INC.

Inventor： PARIKH, Suketu ,  YEOH, Andrew ,  CHOI, Tom S. ,  LEE, Joung Joo ,  INGLE, Nitin K.

IPC: H01L21/311 ,  H01L21/768 ,  H01L21/02

Abstract: Methods open etch stop layers in an integrated environment along with metallization processes. In some embodiments, a method for opening an etch stop layer (ESL) prior to metallization may include etching the ESL with an anisotropic process using direct plasma to form helium ions that are configured to roughen the ESL for a first duration of approximately 10 seconds to approximately 30 seconds, forming aluminum fluoride on the ESL using remote plasma and nitrogen trifluoride gas for a second duration of approximately 10 seconds to approximately 30 seconds, and exposing the ESL to a gas mixture of boron trichloride, trimethylaluminum, and/or dimethylaluminum chloride at a temperature of approximately 100 degrees Celsius to approximately 350 degrees Celsius to remove aluminum fluoride from the ESL and a portion of a material of the ESL for a third duration of approximately 30 seconds to approximately 60 seconds.

公开(公告)号：WO2023015117A1

公开(公告)日：2023-02-09

申请号：PCT/US2022/074152

申请日：2022-07-26

Applicant: APPLIED MATERIALS, INC.

Inventor： PARIKH, Suketu ,  YEOH, Andrew ,  CHOI, Tom S. ,  LEE, Joung Joo ,  INGLE, Nitin K.

IPC: H01L21/67 ,  H01L21/768 ,  H01L21/311

Abstract: In some embodiments, an integrated tool for opening an etch stop layer and performing metallization comprises a first chamber with a remote plasma source, a direct plasma source, and a thermal source configured to open the etch stop layer on a substrate, a second chamber of the integrated tool with dry etch processing configured to pre-clean surfaces exposed by opening the etch stop layer, a third chamber of the integrated tool configured to deposit a barrier layer on the substrate, a fourth chamber of the integrated tool configured to deposit a liner layer on the substrate, and at least one fifth chamber of the integrated tool configured to deposit metallization material on the substrate. The integrated tool may also include a vacuum transfer chamber.

公开(公告)号：WO2023278387A1

公开(公告)日：2023-01-05

申请号：PCT/US2022/035235

申请日：2022-06-28

Applicant: APPLIED MATERIALS, INC.

Inventor： PARIKH, Suketu ,  JANSEN, Alexander ,  LEE, Joung Joo ,  LIU, Lequn

IPC: H01L21/768 ,  H01L21/67167 ,  H01L21/67184 ,  H01L21/67207 ,  H01L21/76807 ,  H01L21/7684 ,  H01L21/76846 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53238

Abstract: Interconnect structures on a substrate have low resistivity and high dopant interfaces. In some embodiments, the structures may have an opening with a sidewall from an upper surface to an underlying metallic layer of copper, a barrier layer of tantalum nitride formed on the sidewall of the opening, a liner layer of cobalt or ruthenium formed on the barrier layer and on the underlying metallic layer, a first copper layer with a dopant with a first dopant content formed on the liner layer and filling a lower portion of the opening to form a via - the first dopant content is approximately 0.5 percent to approximately 10 percent, and a second copper layer with the dopant with a second dopant content formed on the first copper layer and filling the at least one opening - the second dopant content is more than zero to approximately 0.5 percent of the dopant and is less than the first dopant content.

公开(公告)号：WO2023278384A1

公开(公告)日：2023-01-05

申请号：PCT/US2022/035231

申请日：2022-06-28

Applicant: APPLIED MATERIALS, INC.

Inventor： PARIKH, Suketu ,  JANSEN, Alexander ,  LEE, Joung Joo ,  LIU, Lequn

IPC: H01L21/768 ,  H01L21/285 ,  H01L21/02063 ,  H01L21/31053 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/7684 ,  H01L21/76846 ,  H01L21/76882 ,  H01L23/53238

Abstract: Methods for forming interconnects on a substrate with low resistivity and high dopant interfaces. In some embodiments, a method includes depositing a first copper layer with a dopant with a first dopant content of 0.5 percent to 10 percent in the interconnect by sputtering a first copper-based target at a first temperature of zero degrees Celsius to 200 degrees Celsius, annealing the substrate at a second temperature of 200 degrees Celsius to 400 degrees Celsius to reflow the first copper layer, depositing a second copper layer with the dopant with a second dopant content of zero percent to 0.5 percent by sputtering a second copper-based target at the first temperature of zero degrees Celsius to 200 degrees Celsius, and annealing the substrate at a third temperature of 200 degrees Celsius to 400 degrees Celsius to reflow the second copper layer.