公开(公告)号：WO2020076615A1

公开(公告)日：2020-04-16

申请号：PCT/US2019/054557

申请日：2019-10-03

Applicant: MICRO TECHNOLOGY, INC.

Inventor： SILLS, Scott, E. ,  PRALL, Kirk, D. ,  RAMASWAMY, Dural Vishak, Nirmal ,  GANDHI, Ramanathan

IPC: H01L27/24 ,  H01L27/082 ,  H01L27/06 ,  H01L27/11514 ,  H01L27/11597 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/516 ,  H01L29/66969 ,  H01L29/78391 ,  H01L29/78642

Abstract: A device comprises an array comprising rows and columns of elevationally-extending transistors. An access line interconnects multiple of the elevationally-extending transistors along individual of the rows. The transistors individually comprise an upper source/drain region, a lower source/drain region, and a channel region extending elevationally there- between. The channel region comprises an oxide semiconductor. A transistor gate is operatively laterally-proximate the channel region and comprises a portion of an individual of the access lines. Intra-row- insulating material is longitudinally between immediately -intra-row -adjacent of the elevationally-extending transistors. Inter-row-insulating material is laterally between immediately-adjacent of the rows of the elevationally- extending transistors. At least one of the intra-row-insulating material and the inter-row-insulating material comprises void space. Other embodiments, including method embodiments, are disclosed.

公开(公告)号：WO2019202426A1

公开(公告)日：2019-10-24

申请号：PCT/IB2019/052574

申请日：2019-03-28

Applicant: SILANNA ASIA PTE LTD

Inventor： KUSHNER, Vadim ,  BEIKAE, Nima

IPC: H01L27/082 ,  H01L27/02 ,  H01L21/8222 ,  H01L29/73 ,  H01L29/66

Abstract: A lateral transistor tile is formed with first and second collector regions that longitudinally span first and second sides of the transistor tile; and a base region and an emitter region that are between the first and second collector regions and are both centered on a longitudinal midline of the transistor tile. A base-collector current, a collector-emitter current, and a base-emitter current flow horizontally; and the direction of the base-emitter current is perpendicular to the direction of the base-collector current and the collector-emitter current. Lateral BJT transistors having a variety of layouts are formed from a plurality of the tiles and share common components thereof.

公开(公告)号：WO2012171342A1

公开(公告)日：2012-12-20

申请号：PCT/CN2012/070382

申请日：2012-01-16

Applicant: 深圳市力生美半导体器件有限公司 ,  郑凌波 ,  林新春 ,  罗小荣

Inventor： 郑凌波 ,  林新春 ,  罗小荣

IPC: H01L27/082 ,  H01L29/732 ,  H02M7/02

CPC classification number: H01L27/0744 ,  H01L29/73

Abstract: 提供了一种AC-DC开关电源及其功率三极管，该功率三极管包括一作为集电极的衬底（1），在该衬底上形成的相互隔离的至少两个基区（2，4）、在每个基区上形成的一个发射极（3，5）以及与该衬底电连接的集电极引脚（C）、与该些基区电连接的至少两个基极引脚（B1，B2）、与该些发射极电连接的至少两个发射极引脚（E1，E2），该衬底、每个基区、每个基区上的发射极及相应的引脚构成一个三极管单元。该AC-DC开关电源，包括一电源管理电路和与该电源管理电路电连接的开关管，该开关管具有所述功率三极管结构。该AC-DC开关电源可以在控制成本的前提下，确保开关电源的性能。

公开(公告)号：WO2011053926A3

公开(公告)日：2011-06-30

申请号：PCT/US2010054998

申请日：2010-11-01

Applicant: ANALOG DEVICES INC

Inventor： STENSON BERNARD PATRICK ,  BAIN ANDREW DAVID ,  BOWERS DEREK FREDERICK ,  DALY PAUL MALACHY ,  DEIGNAN ANNE MARIA ,  DUNBAR MICHAEL THOMAS ,  MCGUINNESS PATRICK MARTIN ,  LANE WILLIAM ALLAN

IPC: H01L29/08 ,  H01L21/331 ,  H01L21/8222 ,  H01L27/082 ,  H01L29/73 ,  H01L29/732

CPC classification number: H01L29/0821 ,  H01L21/8222 ,  H01L29/66272 ,  H01L29/7317 ,  H01L29/7322

Abstract: A bipolar transistor, comprising a collector (70), a base (92), and an emitter (100), in which the collector (70) comprises a relatively heavily doped region. The bipolar transistor may also comprise a relatively lightly doped region (90) adjacent the base (92). The relatively heavily doped region can be substantially omitted from an intrinsic region (110) of the transistor.

Abstract translation: 一种双极晶体管，包括集电极（70），基极（92）和发射极（100），其中集电极（70）包括相对重掺杂的区域。 双极晶体管还可以包括与基部（92）相邻的相对轻度掺杂的区域（90）。 可以从晶体管的本征区域（110）基本上省略相对重掺杂的区域。

公开(公告)号：WO2006098868A3

公开(公告)日：2007-04-12

申请号：PCT/US2006006814

申请日：2006-02-24

Applicant: LATTICE SEMICONDUCTOR CORP

Inventor： BARTEL ROBERT ,  SMOAK RICHARD ,  AGAM MOSHE ,  MCDONALD ADRIAN

IPC: H01L29/76 ,  H01L27/082 ,  H01L27/095 ,  H01L29/70

CPC classification number: H01L29/6625 ,  H01L27/067 ,  H01L29/0692 ,  H01L29/735

Abstract: In one embodiment of the invention, a bipolar junction transistor (BJT) includes an emitter (216A) comprised of a first doped region doped with a first dopant of a first conductivity type. In addition, a salicide block (224) is disposed over a periphery portion (226) of t first doped region, and a suicide (242A) is formed on an exposed portion of the first doped region inside the periphery portion (226). Such a salicide block (224) prevents formation of salicide down to a base region (210A) in turn preventing leakage current through the base for increased of the BJT.

Abstract translation: 在本发明的一个实施例中，双极结型晶体管（BJT）包括由掺杂有第一导电类型的第一掺杂物的第一掺杂区组成的发射极（216A）。 此外，在第一掺杂区域的周边部分（226）上设置自对准硅化物块（224），并且在周边部分（226）内的第一掺杂区域的暴露部分上形成硅化物（242A）。 这种自对准硅化物块（224）防止防止自底向下形成底部区域（210A），从而防止通过基底的泄漏电流增加BJT。

公开(公告)号：WO2005074549A3

公开(公告)日：2007-02-08

申请号：PCT/US2005002752

申请日：2005-01-31

Applicant: TRIQUINT SEMICONDUCTOR INC

Inventor： APEL THOMAS R ,  MIDDLETON JEREMY R

IPC: H01L27/082 ,  H01L27/102 ,  H01L29/06 ,  H01L29/70 ,  H01L29/737 ,  H01L31/11

CPC classification number: H01L29/737 ,  H01L29/0692

Abstract: The invention pertains to an integrated circuit comprising a bipolar junction transistor (100) in which a base contact region (120) forms a fishbone configuration and an emitter region (110) is adjacent to the periphery of the fishbone configuration.

Abstract translation: 本发明涉及一种集成电路，其包括双极结型晶体管（100），其中基极接触区域（120）形成鱼骨形状，并且发射极区域（110）邻近鱼骨构造的外围。

公开(公告)号：WO2006132714A2

公开(公告)日：2006-12-14

申请号：PCT/US2006/015112

申请日：2006-04-21

Applicant: FREESCALE SEMICONDUCTOR, INC. ,  KHEMKA, Vishnu, K. ,  BOSE, Amitava ,  ZHU, Ronghua

Inventor： KHEMKA, Vishnu, K. ,  BOSE, Amitava ,  ZHU, Ronghua

IPC: H01L27/082

CPC classification number: H01L29/7393 ,  H01L29/063 ,  H01L29/66325

Abstract: A semiconductor component and method of manufacture, including an insulated gate bipolar transistor (IGBT) (100) including a semiconductor substrate (110) having a first conductivity type and buried semiconductor region (115) having a second conductivity type located above the semiconductor substrate. The IGBT further includes a plurality of first semiconductor regions (120) having the first conductivity type, a plurality of second semiconductor regions (130) having the first conductivity type, and a plurality of third semiconductor regions (140) having the second conductivity type. A sinker region (142) having the second conductivity type is disposed in a third semiconductor region and a first semiconductor region during manufacture to define the plurality of regions and tie the buried semiconductor region to the plurality of third semiconductor regions. An emitter (150) having the first conductivity type is disposed in one of the third semiconductor regions, a collector (170) having the first conductivity type is disposed in the other of the third semiconductor regions. A field poly plate (162) is provided and tied to the collector (170). In a particular embodiment, the plurality of third semiconductor regions and the buried semiconductor region deplete the plurality of first semiconductor regions in response to a reverse bias potential applied between the plurality of second semiconductor regions and the plurality of third semiconductor regions.

Abstract translation: 一种包括具有第一导电类型的半导体衬底（110）和位于半导体衬底上方的具有第二导电类型的掩埋半导体区（115）的绝缘栅双极晶体管（IGBT）（100）的半导体元件和制造方法。 IGBT还包括具有第一导电类型的多个第一半导体区域（120），具有第一导电类型的多个第二半导体区域（130）和具有第二导电类型的多个第三半导体区域（140）。 具有第二导电类型的沉降片区域（142）在制造期间设置在第三半导体区域和第一半导体区域中，以限定多个区域并将掩埋半导体区域与多个第三半导体区域相连。 具有第一导电类型的发射极（150）设置在第三半导体区域之一中，具有第一导电类型的集电极（170）设置在第三半导体区域中的另一个中。 提供了现场多晶板（162）并将其连接到集电器（170）。 在特定实施例中，响应于施加在多个第二半导体区域和多个第三半导体区域之间的反向偏置电位，多个第三半导体区域和掩埋半导体区域耗尽多个第一半导体区域。

公开(公告)号：WO2005052997A3

公开(公告)日：2006-09-28

申请号：PCT/US2004038823

申请日：2004-11-19

Applicant: WISCONSIN ALUMNI RESARCH FOUND ,  MA ZHENQIANG ,  JIANG NINGYUE

Inventor： MA ZHENQIANG ,  JIANG NINGYUE

IPC: H01L20060101 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/73 ,  H01L29/737 ,  H01L31/072 ,  H01L27/102 ,  H01L27/082

CPC classification number: H01L29/42304 ,  H01L29/0692 ,  H01L29/41708 ,  H01L29/73 ,  H01L29/7304 ,  H01L29/7378

Abstract: A high-power solid-state transistor structure comprised of a plurality of emitter or gate fingers in a uniform or non-uniform manner to provide improved high power performance is disclosed. Preferably, each of the fingers is associated with a corresponding one of a plurality of sub-cells, the sub-cells being arranged in at least one row. The advantage of the invention is that the structure can be practically implemented and the absolute thermal stability can be maintained for very high power transistors with reduced adverse effects resulting from random variation in the manufacturing and design process.

Abstract translation: 公开了一种以均匀或不均匀的方式由多个发射极或栅极指状构成的高功率固态晶体管结构，以提供改进的高功率性能。 优选地，每个手指与多个子单元中的对应的一个子单元相关联，该子单元布置在至少一行中。 本发明的优点在于，可以实际地实现该结构，并且可以保持对于具有由制造和设计过程中的随机变化导致的不利影响减小的非常高功率晶体管的绝对热稳定性。

公开(公告)号：WO2006098868A2

公开(公告)日：2006-09-21

申请号：PCT/US2006/006814

申请日：2006-02-24

Applicant: LATTICE SEMICONDUCTOR CORPORATION

Inventor： BARTEL, Robert ,  SMOAK, Richard ,  AGAM, Moshe ,  MCDONALD, Adrian

IPC: H01L27/082

CPC classification number: H01L29/6625 ,  H01L27/067 ,  H01L29/0692 ,  H01L29/735

Abstract: In one embodiment of the invention, a bipolar junction transistor (BJT) includes an emitter comprised of a first doped region doped with a first dopant of a first conductivity type. In addition, a salicide block is disposed over a periphery portion of the first doped region, and a salicide is formed on an exposed portion of the first doped region inside the periphery portion. Such a salicide block prevents formation of salicide down to a base region in turn preventing leakage current through the base for increased ß of the BJT.

Abstract translation: 在本发明的一个实施例中，双极结型晶体管（BJT）包括由掺杂有第一导电类型的第一掺杂物的第一掺杂区组成的发射极。 另外，在第一掺杂区域的周边部分设置自对准硅化物块，并且在外围部分的第一掺杂区域的暴露部分上形成硅化物。 这种自杀化合物阻止防止自杀剂向底部区域形成，从而防止通过底部的泄漏电流增加BJT的β。

公开(公告)号：WO2003036724A2

公开(公告)日：2003-05-01

申请号：PCT/EP2002/009703

申请日：2002-08-30

Applicant: INFINEON TECHNOLOGIES AG ,  BOECK, Josef ,  MEISTER, Thomas ,  SCHAEFER, Herbert ,  STENGL, Reinhard

Inventor： BOECK, Josef ,  MEISTER, Thomas ,  SCHAEFER, Herbert ,  STENGL, Reinhard

IPC: H01L27/082

CPC classification number: H01L21/84 ,  H01L21/76264 ,  H01L27/1203

Abstract: Eine Halbleiterstruktur umfasst ein Substrat (10), eine Baulementschicht (18), die an einer Oberfläche (12) des Substrats (10) angeordnet ist, einen Bipolar-Transistor (30a) und ein Halbleiter-Bauelement (30b), die in der Bauelementschicht (18) angeordnet sind, und einen Isolierbereich (60, 62, 64, 66, 68), der an den Bipolar-Transistor (30a) und das Halbleiter-Bauelement (30b) angrenzt, einen Zwischenraum (102) zwischen dem Bipolar-Transistor (30a) und dem Halbleiter-Bauelement (30b) vollständig einnimmt und ein elektrisch isolierendes Material aufweist.

Abstract translation: 半导体结构包括衬底（10），设置在衬底（10）的表面（12）上的器件层（18），双极晶体管（30a）和半导体 设置在器件层（18）中的器件（30b）和与双极晶体管（30a）和半导体器件（30b）相邻的隔离区（60,62,64,66,68） 完全占据双极晶体管（30a）和半导体器件（30b）之间的间隙（102）并且具有电绝缘材料。