公开(公告)号：WO2021259478A1

公开(公告)日：2021-12-30

申请号：PCT/EP2020/067773

申请日：2020-06-25

Applicant: HUAWEI TECHNOLOGIES CO., LTD. ,  BADAROGLU, Mustafa

Inventor： BADAROGLU, Mustafa

IPC: H01L29/06 ,  B82Y10/00 ,  H01L29/423 ,  H01L29/775 ,  H01L21/8238 ,  H01L27/088 ,  H01L21/336 ,  H01L21/823412 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/78696

Abstract: A method of producing Gate-AII-Around (GAA) devices on a semiconductor wafer. The method includes defining a first area and etching the first area to obtain a first space for the first GAA device. The method further includes applying a first stack in the first space, by alternatingly applying nanosheets and spacer elements and applying a final layer of the etchable material. The method includes defining a second area and etching the second area to obtain a second space for the second GAA device. The method further includes applying a second stack in the second space, and applying a final layer of the etchable material. Notably, the first stack and the second stack differ from one another with respect to one or more of the number of nanosheets, the thickness of each nanosheet, and the height of the spacer elements.

公开(公告)号：WO2021259477A1

公开(公告)日：2021-12-30

申请号：PCT/EP2020/067772

申请日：2020-06-25

Applicant: HUAWEI TECHNOLOGIES CO., LTD. ,  BADAROGLU, Mustafa

Inventor： BADAROGLU, Mustafa

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L2224/03845 ,  H01L2224/04105 ,  H01L2224/05609 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/08145 ,  H01L2224/08147 ,  H01L2224/80006 ,  H01L2224/80013 ,  H01L2224/80047 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2225/06593 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L24/94 ,  H01L24/96 ,  H01L25/0657 ,  H01L25/50

Abstract: A method of stacking semiconductor components, to obtain a semiconductor wafer assembly, and for forming a semiconductor die assembly therefrom, is provided. The method comprises providing a first wafer comprising at least a first and a second die in a first and a second position, respectively; providing at least a third and a fourth die, to be stacked on the first and the second die, respectively; placing the third and fourth die on a carrier wafer in positions matching at least a part of the first and second position, respectively; applying insulating material on the carrier wafer outside of the third and the fourth dies; and placing the carrier wafer on the first wafer to obtain a first die stack of the first and third dies and a second die stack of the second and fourth dies, causing bonding of the first and third dies and the second and fourth dies, respectively.

公开(公告)号：WO2021259479A1

公开(公告)日：2021-12-30

申请号：PCT/EP2020/067774

申请日：2020-06-25

Applicant: HUAWEI TECHNOLOGIES CO., LTD. ,  BADAROGLU, Mustafa

Inventor： BADAROGLU, Mustafa

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/535 ,  H01L21/74 ,  H01L21/743 ,  H01L21/76897 ,  H01L23/5286

Abstract: A semiconductor device includes a substrate having one or more active regions and a power rail located in an isolation trench in the semiconductor device. The active region extends further from the substrate than the power rail. The semiconductor device further includes one or more source/drain (S/D) contacts having a top wall extending along a surface of the active region facing away from the substrate and a side wall extending along a surface of the active region on the same side as the power rail but farther from the substrate. The semiconductor device includes a via trench adjacent to the side wall. The trench includes a via which is on a first side in electrical contact with a surface of power rail facing away from substrate. On another side, perpendicular to first side, the via is conformal to and in electrical contact with the side wall of the S/D contact.

公开(公告)号：WO2021259476A1

公开(公告)日：2021-12-30

申请号：PCT/EP2020/067771

申请日：2020-06-25

Applicant: HUAWEI TECHNOLOGIES CO., LTD. ,  BADAROGLU, Mustafa

Inventor： BADAROGLU, Mustafa

IPC: G06F30/30 ,  H03K19/096 ,  H03K19/018585

Abstract: A method of designing a datapath between two memory units in a semiconductor component. The datapath includes two or more positions for cells, each cell having a rising edge and a falling edge. The method includes selecting for each of the two or more positions a cell type from a library comprising available cells. Each available cell is able to perform an operation, and each cell having a P region and an N region and being P/N imbalanced. The cell type is selected in dependence of a switching point of a preferred edge to be used in the operation. The preferred edge is either the rising edge or the falling edge of the cell.

公开(公告)号：WO2007088211A1

公开(公告)日：2007-08-09

申请号：PCT/EP2007/051052

申请日：2007-02-02

Applicant: INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM VZW ,  BADAROGLU, Mustafa

Inventor： BADAROGLU, Mustafa

IPC: H03K5/13 ,  H03H11/26

CPC classification number: H03K5/131 ,  H03K5/133 ,  H03K7/04 ,  H04B1/7183

Abstract: The invention relates to a device comprising at least one delay line for applying a variable delay to a clock signal and a controller for controlling the variable delay of the delay line. Each delay line comprises a plurality of concatenated delay banks which provide different delay values with respect to each other, a bypass parallel over each of said delay banks, and switching elements associated with each of said delay banks for selecting either the respective delay bank or the respective bypass. Each of said delay banks is provided with a delay bank status indicator for indicating propagation of the clock signal through the delay bank towards the controller. The controller is provided for taking the indicated propagation of the clock signal into account upon setting said switching elements. The device of the invention is amongst others suited for use in Ultra Wide Band (UWB) receiving or transmitting devices, in particular those devices, designed for low power consumption, by enabling power on and off switching of parts of said device like analog to digital converters and integrators, during timing windows.

Abstract translation: 本发明涉及一种装置，包括至少一个用于向时钟信号施加可变延迟的延迟线和控制器，用于控制延迟线的可变延迟。 每个延迟线包括多个级联延迟组，它们相对于彼此提供不同的延迟值，在每个所述延迟组上并联的旁路，以及与每个所述延迟组相关联的开关元件，用于选择相应的延迟组或 各自的旁路。 所述延迟组中的每一个被提供有延迟组状态指示符，用于指示时钟信号通过延迟组向控制器的传播。 设置控制器用于在设置所述开关元件时考虑所指示的时钟信号的传播。 本发明的装置尤其适合用于超宽带（UWB）接收或发射设备，特别是那些设计用于低功耗的设备，通过启用和断开所述设备的部件的类似模数转换 转换器和积分器。

公开(公告)号：WO2005078608A2

公开(公告)日：2005-08-25

申请号：PCT/BE2005/000020

申请日：2005-02-14

Applicant: INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM VZW ,  BADAROGLU, Mustafa

Inventor： BADAROGLU, Mustafa

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F1/04

Abstract: The present relates to a digital sub-circuit suitable for embedding in an at least partially digital circuit for minimising the influence of another digital sub-circuit on the at least partially digital circuit, the other digital sub-circuit being part of the at least partially digital circuit. The influence of the other digital sub-circuit may for example be the introduction of ground bounce by switching of the other digital sub-circuit. The present invention furthermore relates to an at least partially digital circuit comprising such a digital sub-circuit for minimising the influence of another digital sub-circuit to the at least partially digital circuit and to a method for reducing the influence of another digital sub-circuit to an at least partially digital circuit.

Abstract translation: 本发明涉及适于嵌入到至少部分数字电路中的数字子电路，以最小化另一数字子电路对至少部分数字电路的影响，另一数字子电路是至少部分数字子电路的一部分 数字电路。 另一个数字子电路的影响可能是例如通过切换另一个数字子电路来引入接地反弹。 本发明还涉及至少部分数字电路，其包括用于最小化另一数字子电路对至少部分数字电路的影响的数字子电路以及用于减小另一数字子电路的影响的方法 至少部分数字电路