公开(公告)号：WO2012176250A1

公开(公告)日：2012-12-27

申请号：PCT/JP2011/006995

申请日：2011-12-14

Applicant: パナソニック株式会社 ,  長沢 俊伸 ,  徳丸 美智子 ,  生駒 平治

Inventor： 長沢　俊伸 ,  徳丸　美智子 ,  生駒　平治

IPC: H03K5/08 ,  H03K17/687 ,  H03K19/01 ,  H03M1/74

CPC classification number: H03M1/66 ,  H03K3/013 ,  H03K17/162 ,  H03K19/0185 ,  H03K19/09432 ,  H03K19/09441 ,  H03K19/20

Abstract: 　電流源（３）に各々の一端が接続された第１と第２のスイッチ素子（１，２）を備えた差動スイッチ回路（４）を駆動する差動スイッチ駆動回路（１０）であって、電流源（５）と、差動入力端子対（Ａ，Ｂ）と差動出力端子対（Ｘ，Ｙ）とを有して共通接続部を電流源（５）に接続したトランジスタ対を有する電流制御回路（６）と、差動出力端子対（Ｘ，Ｙ）にそれぞれ接続された負荷素子（７，８）とを備える。差動スイッチ駆動回路（１０）は、差動入力端子対（Ａ，Ｂ）の電圧に応じて、それぞれの値が略一定な２値の定常状態と２値間を遷移する過渡状態とを有した出力電圧を差動出力端子対（Ｘ，Ｙ）に出力する。この際、差動出力電圧の定常状態における負荷素子（７，８）に流れる電流値の和が、過渡状態における負荷素子（７，８）に流れる電流値の和と異なるように、トランジスタ対に流れる電流を制御する。

Abstract translation: 一种用于驱动具有第一和第二开关元件（1,2）的差分开关电路（4）的差分开关驱动电路（10），每个开关元件的一端连接到电流源（3），包括电流源 5），电流控制电路（6），其包括具有一对差分输入端子（A，B）和一对差分输出端子（X，Y）的一对晶体管，并且具有连接到电流的公共连接部分 源极（5）和负载元件（7,8），每个负载元件连接到该对差分输出端子（X，Y）。 差分开关驱动电路（10）根据该差分输入端子（A，B）的电压，向一对差动输出端子（X，Y）输出具有稳定状态的输出电压， 每个基本上是恒定的，并且该值在两个值之间转变的过渡状态。 此时，流经该对晶体管的电流被控制成使得在差分输出电压的稳定状态下流经负载元件（7,8）的电流值与电流值之和不同 在过渡状态下流过负载元件（7,8）。

公开(公告)号：WO1995026078A1

公开(公告)日：1995-09-28

申请号：PCT/SE1995000280

申请日：1995-03-20

Applicant: TELEFONAKTIEBOLAGET LM ERICSSON

Inventor： TELEFONAKTIEBOLAGET LM ERICSSON ,  HEDBERG, Mats, Olof, Joakim

IPC: H03K19/01

CPC classification number: G05F3/262

Abstract: The present invention comprises a signal-receiving and signal-processing unit connected to one or several conductors (L2) adapted to transmit information-carrying signals in the form of voltage pulses. A conductor (L2) is connected to a transistor (NT21) belonging to a signal-receiving circuit, to have an effect upon a current (I2) by using variations in the voltage pulses and the voltage value of a pulse. The current is in the form of pulses passing through the transistor (NT21). The current is generated by the voltage pulse variations and a voltage level, and the current is adapted to an information-carrying form (L3) in a signal-processing circuit (3). The transistor (NT21) belonging to the signal-receiving circuit is coordinated with at least one other transistor (NT23) to form a current mirror. The ability of the signal-receiving circuit to receive, detect, and process the signals is adjustable through a current-generating circuit (10) such that an increasing current value (IT) provides detection of a voltage pulse at an increased transfer rate and vice versa.

Abstract translation: 本发明包括一个连接到一个或多个导体（L2）的信号接收和信号处理单元，适用于传送电压脉冲形式的信息传送信号。 导体（L2）连接到属于信号接收电路的晶体管（NT21），通过使用电压脉冲和脉冲的电压值的变化来影响电流（I2）。 电流是通过晶体管（NT21）的脉冲的形式。 电流由电压脉冲变化和电压电平产生，并且电流适应于信号处理电路（3）中的信息传送形式（L3）。 属于信号接收电路的晶体管（NT21）与至少一个其它晶体管（NT23）协调以形成电流镜。 信号接收电路接收，检测和处理信号的能力可通过电流产生电路（10）进行调节，使得增加的电流值（IT）以增加的传输速率提供电压脉冲的检测 反之亦然。

公开(公告)号：WO2014106197A1

公开(公告)日：2014-07-03

申请号：PCT/US2013/078337

申请日：2013-12-30

Applicant: DIALIGHT CORPORATION

Inventor： HEBBORN, Kevin A.

IPC: H03K17/16 ,  H03K19/01

CPC classification number: H05B33/0842 ,  H02M3/04 ,  H05B33/0815 ,  Y02B20/347

Abstract: The present disclosure is directed to an input impedance control circuit. In one embodiment, the automatic input impedance control circuit includes a circuit controller that comprises a module for calculating an impedance and a control logic module, wherein the control logic module provides a current enable signal and a current control output signal, a driver in communication with the circuit controller for receiving the current enable signal and the current control output signal, an input voltage sensing circuit in communication with the module for calculating the impedance and the control logic module and an input current sensing circuit in communication with the module for calculating the impedance.

Abstract translation: 本公开针对输入阻抗控制电路。 在一个实施例中，自动输入阻抗控制电路包括电路控制器，其包括用于计算阻抗的模块和控制逻辑模块，其中控制逻辑模块提供电流使能信号和电流控制输出信号，与 用于接收电流使能信号和电流控制输出信号的电路控制器，与用于计算阻抗的模块通信的输入电压感测电路和控制逻辑模块以及与模块通信的输入电流感测电路，用于计算阻抗 。

公开(公告)号：WO2009088695A2

公开(公告)日：2009-07-16

申请号：PCT/US2008/087455

申请日：2008-12-18

Applicant: SanDisk Corporation ,  LAI, Po-Shen ,  SABHARANJAK, Vaibhavi ,  HERON, Ralph ,  IGUELMAMENE, Lakhdar

Inventor： LAI, Po-Shen ,  SABHARANJAK, Vaibhavi ,  HERON, Ralph ,  IGUELMAMENE, Lakhdar

IPC: H03K17/08 ,  H03K19/01

CPC classification number: H03K19/018585 ,  H03K19/017581

Abstract: An integrated circuit (IC) includes an output driver circuit portion that is electrically configurable, via a configuration input, to operate in either a first mode or a second mode corresponding to an indication of a condition of the IC, such as a supply voltage indication, the first mode and the second mode having different drive characteristics. A configuration interface circuit portion as part of the improved IC is adapted to selectively override the configuration input to configure operation of the output driver circuit portion in either the first mode or the second mode based on a drive strength control input, regardless of the condition of the IC.

Abstract translation: 集成电路（IC）包括输出驱动器电路部分，其经由配置输入可电气配置，以对应于IC的状态的指示的第一模式或第二模式操作，诸如电源电压指示 第一模式和第二模式具有不同的驱动特性。 作为改进IC的一部分的配置接口电路部分适于选择性地覆盖配置输入以基于驱动强度控制输入来配置在第一模式或第二模式中的输出驱动器电路部分的操作，而不管 IC。

公开(公告)号：WO1991018448A1

公开(公告)日：1991-11-28

申请号：PCT/US1991003192

申请日：1991-05-08

Applicant: SIARC

Inventor： SIARC ,  EL GAMAL, Abbas

IPC: H03K19/01

CPC classification number: H03K19/09448

Abstract: In one embodiment of the invention, a CMOS device (32) inverts an input signal and provides this inverted input signal into the base of an NPN bipolar transistor (Q3) whose collector is coupled to a positive power supply voltage. The input signal coupled to the input of the CMOS device is also coupled to the gate of a large N-channel MOSFET (Q4) having its drain coupled to the emitter of the bipolar transistor and its source coupled to ground. The common node (36) of the bipolar transistor and the N-channel MOSFET provides the output signal of the driver. This driver uses much less area than a standard two-bipolar transistor BiCMOS driver with substantially equal performance.

公开(公告)号：WO2009091928A2

公开(公告)日：2009-07-23

申请号：PCT/US2009/031160

申请日：2009-01-15

Applicant: ROBUST CHIP, INC. ,  LILJA, Klas, Olof

Inventor： LILJA, Klas, Olof

IPC: H03K19/173 ,  H03K19/01

CPC classification number: G06F17/5022 ,  G06F17/5068 ,  G06F2217/12 ,  H03K19/0033 ,  H03K19/00338 ,  H03K19/20 ,  Y02P90/265

Abstract: This invention comprises a layout method to effectively protect logic circuits against soft errors (non-destructive errors) and circuit cells, with layout, which are protected against soft errors. In particular, the method protects against cases where multiple nodes in circuit are affected by a single event. These events lead to multiple errors in the circuit, and while several methods exist to deal with single node errors, multiple node errors are very hard to deal with using any currently existing protection methods. The method is particularly useful for CMOS based logic circuits in modern technologies (

Abstract translation: 本发明包括一种布局方法，用于有效保护逻辑电路免受软错误（非破坏性错误）和电路单元的影响，其布局受到保护以防止软错误。 特别是，该方法可以防止电路中的多个节点受到单个事件影响的情况。 这些事件导致电路出现多重错误，虽然存在几种方法来处理单节点错误，但多节点错误很难处理使用任何现有的保护方法。 该方法对于现代技术（<90nm）中基于CMOS的逻辑电路特别有用，其中多节点脉冲的发生变高（由于高集成度）。 它采用独特的布局配置，使电路免受单个事件产生的软错误的影响。

公开(公告)号：WO2009061913A2

公开(公告)日：2009-05-14

申请号：PCT/US2008082625

申请日：2008-11-06

Applicant: ELASTIX CORP ,  CORTADELLA JORDI ,  SINGHAL VIGYAN ,  TUNCER EMRE

Inventor： CORTADELLA JORDI ,  SINGHAL VIGYAN ,  TUNCER EMRE

IPC: H03K19/096 ,  H03K19/01 ,  H04J3/06

CPC classification number: H03L7/00 ,  G06F17/505 ,  G06F2217/14 ,  H03K19/20

Abstract: A system for automatically transforming a given synchronous circuit description into an equivalent and provably correct desynchronized circuit description. Included in the automated transformation are techniques a variability-aware controller using a two-phase protocol, techniques for synthesizing a variability-aware controller using gated clocks and testability circuits, techniques for synthesizing a variability-aware controller optimized for performance, techniques for initializing the synthesized controller, techniques for dynamically minimizing power requirements, and techniques for interfacing the desynchronized circuit with external synchronous circuits. Also disclosed are techniques for implementing a system for automatically transforming a synchronous circuit description into an equivalent and provably correct desynchronized circuit description within the context of an electronic design automation design flow. Exemplary circuits used in the application of the aforementioned techniques are provided. Application of mathematical models and techniques used for proving equivalence between the input description and the resulting desynchronized circuit are presented and explained.

Abstract translation: 用于自动将给定的同步电路描述转换为等效且可证实正确的去同步电路描述的系统。 自动转换中包括技术：使用两阶段协议的可变性感知控制器，使用门控时钟和可测试性电路合成可变性感知控制器的技术，用于综合性能优化的可变性感知控制器的技术，用于初始化 合成控制器，用于动态最小化功率要求的技术以及用于将去同步电路与外部同步电路接口的技术。 还公开了用于实现用于在电子设计自动化设计流程的上下文中将同步电路描述自动转换为等效且可证实正确的去同步电路描述的系统的技术。 提供了在前述技术的应用中使用的示例性电路。 介绍并解释了用于证明输入描述与所产生的去同步电路之间的等价性的数学模型和技术的应用。

公开(公告)号：WO2004047294A2

公开(公告)日：2004-06-03

申请号：PCT/IB0305166

申请日：2003-11-14

Applicant: KONINKL PHILIPS ELECTRONICS NV ,  PHILIPS CORP ,  DE LANGEN KLAAS-JAN

Inventor： DE LANGEN KLAAS-JAN

IPC: H03K17/16 ,  H03K19/01

CPC classification number: H03F1/02 ,  H03F1/30 ,  H03F3/345 ,  H03K17/166

Abstract: An amplifier/driver (40) for a bus has an output transistor (M1) that is controlled by a controlled current source (I1). In a quiescent state, the output transistor is configured as part of a current mirror (M1, M11) that maintains a gate-source voltage on the output transistor above the threshold voltage of the output transistor, thereby providing a fast turnon turn-on time. In an active state, the controlled current source provides a substantially constant current to the output transistor to achieve a controlled slew-rate, then reduces the current to the output transistor when a desired output voltage level is achieved. To improve power efficiency, a second controlled current source (I2) provides current to the output load when the desired output voltage level is achieved. To minimize transients, a class-AB control circuit (710) provides a minimum bias current to the output transistor, to prevent it from turning off when the desired output voltage level is achieved.

Abstract translation: 用于总线的放大器/驱动器（40）具有由受控电流源（I1）控制的输出晶体管（M1）。 在静止状态下，输出晶体管被配置为保持输出晶体管的阈值电压以上的输出晶体管上的栅极 - 源极电压的电流镜（M1，M11）的一部分，从而提供快速的开启导通时间 。 在激活状态下，受控电流源向输出晶体管提供基本上恒定的电流以实现受控的转换速率，然后当达到期望的输出电压电平时减小流向输出晶体管的电流。 为了提高功率效率，当达到期望的输出电压电平时，第二受控电流源（I2）向输出负载提供电流。 为了使瞬变最小化，AB类控制电路（710）向输出晶体管提供最小偏置电流，以在达到期望的输出电压电平时防止其关断。

公开(公告)号：WO1994024763A1

公开(公告)日：1994-10-27

申请号：PCT/US1994003690

申请日：1994-04-07

Applicant: XILINX, INC.

Inventor： XILINX, INC. ,  CHIANG, David

IPC: H03K19/01

CPC classification number: H03K19/17784 ,  H03K19/0016 ,  H03K19/018585 ,  H03K19/17704

Abstract: A programmable circuit is provided with a number of current regulating circuits, such as sense amplifiers, by which the user can regulate the amount of current drawn by any of a number of circuit functions within the programmable circuit. Additional current regulating circuits are associated with circuit elements which can be programmably shared between one or more circuit functions. The user can therefore programmably control the current consumption, and thereby the speed, of each circuit function as well as circuit functions interacting via the shared circuit elements.

Abstract translation: 可编程电路设有多个电流调节电路，例如读出放大器，用户可以通过该电流调节电路调节由可编程电路内的多个电路功能中的任何一个引出的电流量。 附加的电流调节电路与可在一个或多个电路功能之间可编程共享的电路元件相关联。 因此，用户可以可编程地控制每个电路功能的电流消耗以及由此的速度，以及经由共享电路元件交互的电路功能。

公开(公告)号：WO1989005547A1

公开(公告)日：1989-06-15

申请号：PCT/US1988000485

申请日：1988-02-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  BOUDON, Gérard ,  MOLLIER, Pierre ,  ONG, Ieng ,  AIPPERSPACH, Anthony, Gus ,  DANSKY, Allan, Harvey ,  VAN PHAN, Nghia ,  PLUCHINO, Biagio ,  ZIER, Steven, John ,  ZUCKERMAN, Adrian

Inventor： INTERNATIONAL BUSINESS MACHINES CORPORATION

IPC: H03K19/01

CPC classification number: H03K19/013 ,  H03K19/01707 ,  H03K19/09448 ,  H03K19/215

Abstract: A multi emitter multi input BICMOS NAND circuit (30) is provided wherein an output node OUT connected to an output terminal (33) is coupled between pull up (31) and pull down (32) blocks. The pull up block (31) is comprised of a plurality of identical basic cells, each comprised of a CMOS inverter (C31, C32) driving an NPN pull up transistor (T31, T32) mounted as an emitter follower. Logic signals (A31, A32) are applied on the input of the inverters (C31, C32), and the inverted signal (A(Boolean not)3(Boolean not)1(Boolean not), A(Boolean not)3(Boolean not)2(Boolean not)) is available at the emitter of the emitter follower which corresponds to the output of the cell. All outputs are tied altogether to perform an OR function and are connected to said output terminal (33) to have a multi emitter like circuit. The pull down block (32) in this embodiment is comprised of 2 FETs (F31, F32) serially connected between said output node OUT and a discharge device such as a feedback NFET (Z) the gate of which is connected to said output node OUT. These 2 FETs are for driving an NPN pull down transistor (T2), the collector of which is also connected to the output node OUT.