公开(公告)号：WO2023088645A1

公开(公告)日：2023-05-25

申请号：PCT/EP2022/079819

申请日：2022-10-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  IBM UNITED KINGDOM LIMITED

Inventor： ZHANG, Jingyun ,  ANDO, Takashi ,  LEE, ChoongHyun ,  REZNICEK, Alexander

IPC: H01L29/775 ,  H01L27/088 ,  H01L21/336 ,  H01L29/06 ,  H01L29/51 ,  H01L21/8234 ,  B82Y10/00

Abstract: MULTI-VT NANOSHEET DEVICESA method is presented for attaining different gate threshold voltages across a plurality of field effect transistor (FET) devices without patterning between nanosheet channels. The method includes forming a first set of nanosheet stacks having a first intersheet spacing, forming a second set of nanosheet stacks having a second intersheet spacing, where the first intersheet spacing is greater than the second intersheet spacing, depositing a high-k (HK) layer within the first and second nanosheet stacks, depositing a material stack that, when annealed, creates a crystallized HK layer in the first set of nanosheet stacks and an amorphous HK layer in the second nanosheet stacks, depositing a dipole material, and selectively diffusing the dipole material into the amorphous HK layer of the second set of nanosheet stacks to provide the different gate threshold voltages for the plurality of FET devices.

公开(公告)号：WO2023081966A1

公开(公告)日：2023-05-19

申请号：PCT/AU2022/051338

申请日：2022-11-10

Applicant: MONASH UNIVERSITY

Inventor： FUHRER, Michael Sears

IPC: H03K17/30 ,  H01L27/088 ,  H01L27/108 ,  H01L29/51 ,  H01L29/66 ,  H01L29/745 ,  H01L29/78 ,  H01L29/92 ,  H01L49/00

Abstract: Disclosed herein is A structure comprising: a top gate electrode and a bottom gate electrode, a channel layer formed from a channel material with a band gap modulable by electric field, the channel layer being electrically insulated from the top gate electrode and the bottom gate electrode and being located adjacent to at least one layer of a negative capacitance material.

公开(公告)号：WO2023081699A1

公开(公告)日：2023-05-11

申请号：PCT/US2022/079138

申请日：2022-11-02

Applicant: MICRON TECHNOLOGY, INC.

Inventor： YANG, Hyuck Soo ,  KIM, Byung Yoon ,  YANG, Yong Mo ,  SRIVASTAVA, Shivani

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/51 ,  H01L29/423 ,  H01L29/66

Abstract: Fin field effect transistors (FinFETs) having various different thicknesses of gate oxides and related apparatuses, methods, and computing systems are disclosed. An apparatus includes first FinFETs, second FinFETs, and third FinFETs. The first FinFETs include a first gate oxide material, a second gate oxide material, and a third gate oxide material. The second FinFETs include the second gate oxide material and the third gate oxide material. The third FinFETs include the third gate oxide material. A method includes forming the first gate oxide material on first fins, second fins, and third fins; removing the first gate oxide material from the second fins and the third fins; forming a second gate oxide material over the first fins, the second fins, and the third fins; and removing the second gate oxide material from the third fins.

公开(公告)号：WO2023285555A1

公开(公告)日：2023-01-19

申请号：PCT/EP2022/069644

申请日：2022-07-13

Applicant: HITACHI ENERGY SWITZERLAND AG

Inventor： GUPTA, Gaurav ,  DE-MICHIELIS, Luca ,  VITALE, Wolfgang Amadeus

IPC: H01L29/51 ,  H01L29/739 ,  H01L29/78 ,  H01L21/336

Abstract: In at least one embodiment, the power semiconductor device (1) comprises: - a semiconductor body (2) having a source region (21) of a first conductivity type and a well region (22) of a second conductivity type different from the first conductivity type, and the well region (22) comprises a channel region (220) starting directly at the source region (21), and - a gate insulator (4) directly between the semiconductor body (2) and a gate electrode (31), wherein the gate insulator (4) has a non-uniform gate dielectric constant profile along the channel region (220), such that a relative dielectric constant (εox) of the gate insulator (4) is lowest in a first section (61) of the channel region (220) remote from the source region (21).

公开(公告)号：WO2022250400A1

公开(公告)日：2022-12-01

申请号：PCT/KR2022/007297

申请日：2022-05-23

Applicant: 에스케이트리켐 주식회사 ,  에스케이하이닉스 주식회사

Inventor： 박용주 ,  김동수 ,  김상호 ,  송기창 ,  오한솔 ,  홍창성 ,  이상경 ,  장동학 ,  문지원 ,  이정엽 ,  남혜원

IPC: C23C16/40 ,  C23C16/455 ,  C23C16/18 ,  C23C16/448 ,  C07F5/00 ,  C07F17/00 ,  H01L49/02 ,  H01L29/51

Abstract: 본 발명은 화학식 1로 표시되는 반도체 박막 형성용 금속 전구체 화합물 및 이를 이용하여 형성된 금속 함유 박막에 관한 것이다.

公开(公告)号：WO2022151670A1

公开(公告)日：2022-07-21

申请号：PCT/CN2021/103726

申请日：2021-06-30

Applicant: 长鑫存储技术有限公司

Inventor： 杨蒙蒙 ,  白杰

IPC: H01L21/336 ,  H01L21/28 ,  H01L29/423 ,  H01L29/51 ,  H01L29/78 ,  H01L27/108

Abstract: 本申请提供一种半导体结构的制造方法和半导体结构，涉及半导体制造技术领域，旨在解决现有的半导体结构制造过程中的热预算较高，且炉管的无定形硅层影响功函数层对晶体管的功函数调节过程的问题。本申请的半导体结构的制造方法包括形成第一堆栈层；在第一堆栈层上设置牺牲层。热退火处理第一堆栈层和牺牲层，第一堆栈层形成第二堆栈层。去除牺牲层和第二堆栈层中的功函数复合层和第一导电层，保留第二堆栈层中的衬底、第二界面层和高介电常数层。在高介电常数层上形成栅极层。本申请能够优化半导体结构的功函数调整过程，提升半导体结构的性能。

公开(公告)号：WO2022055680A1

公开(公告)日：2022-03-17

申请号：PCT/US2021/046555

申请日：2021-08-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： PULUGURTHA, Srinivas ,  YANG, Litao ,  LIU, Haitao ,  KARDA, Kamal, M.

IPC: H01L29/51 ,  H01L29/78 ,  H01L27/108 ,  H01L27/1159

Abstract: Some embodiments include integrated memory. The integrated memory includes a first series of first conductive structures and a second series of conductive structures. The first conductive structures extend along a first direction. The second conductive structures extend along a second direction which crosses the first direction. Pillars of semiconductor material extend upwardly from the first conductive structures. Each of the pillars includes a lower source/drain region, an upper source/drain region, and a channel region between the lower and upper source/drain regions. The lower source/drain regions are coupled with the first conductive structures. Insulative material is adjacent sidewall surfaces of the pillars. The insulative material includes ZrOx, where x is a number greater than 0. The second conductive structures include gating regions which are spaced from the channel regions by at least the insulative material. Storage elements are coupled with the upper source/drain regions.

公开(公告)号：WO2022054697A1

公开(公告)日：2022-03-17

申请号：PCT/JP2021/032356

申请日：2021-09-02

Applicant: パナソニックＩＰマネジメント株式会社

Inventor： 佐々木　隆志 ,  田口　誠二 ,  長崎　純久 ,  瀧澤　俊幸

IPC: H01L21/316 ,  C04B35/01 ,  C23C14/08 ,  C23C14/34 ,  H01B3/10 ,  H01G4/10 ,  H01G4/33 ,  H01L21/283 ,  H01L27/04 ,  H01L29/51 ,  H01L29/78

Abstract: 絶縁体の耐電圧にばらつきを生じにくい、酸化物絶縁体膜を提供する。酸化物絶縁体膜（１０）は、第１の金属酸化物（１）と、第２の金属酸化物（２）とを含有する。第２の金属酸化物（２）の電気伝導率は、第１の金属酸化物（１）の電気伝導率よりも低い。酸化物絶縁体膜（１０）は、第２の金属酸化物（２）を含んで構成されるマトリクス中に第１の金属酸化物（１）が分散することで構成されている。

公开(公告)号：WO2022010824A1

公开(公告)日：2022-01-13

申请号：PCT/US2021/040415

申请日：2021-07-06

Applicant: CREE, INC.

Inventor： LICHTENWALNER, Daniel Jenner

IPC: H01L29/16 ,  H01L29/423 ,  H01L29/51 ,  H01L29/78 ,  H01L21/04 ,  H01L29/06 ,  H01L29/739 ,  H01L21/336

Abstract: A semiconductor device includes a semiconductor layer structure that comprises silicon carbide, a gate dielectric layer on the semiconductor layer structure, the gate dielectric layer including a base gate dielectric layer that is on the semiconductor layer structure and a capping gate dielectric layer on the base gate dielectric layer opposite the semiconductor layer structure, and a gate electrode on the gate dielectric layer opposite the semiconductor layer structure. A dielectric constant of the capping gate dielectric layer is higher than a dielectric constant of the base gate dielectric layer.

公开(公告)号：WO2021086788A1

公开(公告)日：2021-05-06

申请号：PCT/US2020/057380

申请日：2020-10-26

Applicant: APPLIED MATERIALS, INC.

Inventor： HUNG, Steven C. ,  COLOMBEAU, Benjamin ,  DUBE, Abhishek ,  KUNG, Sheng-Chin ,  LIU, Patricia M. ,  BEVAN, Malcolm J. ,  SWENBERG, Johanes

IPC: H01L21/28 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/51 ,  H01L29/66

Abstract: Processing methods may be performed to produce semiconductor structures that may include a high-k dielectric material. The methods may include forming a silicon layer over a semiconductor substrate. The semiconductor substrate may include silicon germanium. The methods may include oxidizing a portion of the silicon layer to form a sacrificial oxide while maintaining a portion of the silicon layer in contact with the semiconductor substrate. The methods may include removing the sacrificial oxide. The methods may include oxidizing the portion of the silicon layer in contact with the semiconductor substrate to form an oxygen-containing material. The methods may include forming a high-k dielectric material overlying the oxygen-containing material.