公开(公告)号：WO2023062415A1

公开(公告)日：2023-04-20

申请号：PCT/IB2021/059462

申请日：2021-10-14

Applicant: WILIOT, LTD.

Inventor： YEHEZKELY, Alon ,  KUPFERMAN, Sagi ,  YOGEV, Ido

IPC: G06K19/077 ,  G06K19/07 ,  H03K17/22

Abstract: A wakeup circuit operable in a low-power wireless device is provided. The wakeup circuit includes at least one radio frequency rectifier configured to output a rising transient voltage in response to existence of a RF signal received at an antenna of the wireless device; and a detector configured to output a wakeup signal when an input voltage level of the detector is higher than a reference voltage signal, wherein a signal output by the detector upon detection of a wakeup signal causes resetting each of the at least one rectifier upon detection of the wakeup signal; and wherein the wakeup circuit is coupled to an antenna interface of the wireless device.

公开(公告)号：WO2022067739A1

公开(公告)日：2022-04-07

申请号：PCT/CN2020/119598

申请日：2020-09-30

Applicant: 深圳市汇顶科技股份有限公司

Inventor： 杨江

IPC: H03K17/22

Abstract: 一种上电复位电路，包括：带隙基准电路(11)、电流比较器(12)和电压比较电路(13)，带隙基准电路(11)、电流比较器(12)及电压比较电路(13)均由电压源供电；其中，带隙基准电路(11)的第一输出端与电流比较器(12)的控制端连接；电流比较器(12)的第一电流输入端及第二电流输入端分别接入第一电流信号和第二电流信号，电流比较器(12)的输出端与电压比较电路(13)的控制端连接；电压比较电路(13)的第一输入端与带隙基准电路(11)的第一输出端连接，电压比较电路(13)的第二输入端接入用于指示来自于电压源电压大小的信号，电压比较电路(13)的输出端用于输出复位信号。避免在基准产生电路不稳定时输出复位信号，导致出现错误，减少上电过程中的误触发，增加了上电的可靠性。

公开(公告)号：WO2022010754A1

公开(公告)日：2022-01-13

申请号：PCT/US2021/040222

申请日：2021-07-02

Applicant: INFINEON TECHNOLOGIES LLC

Inventor： GEYARI, Eran ,  SHLOMO, Oren ,  SOFER, Yair ,  HARUSH, Avri

IPC: H03K17/22 ,  G11C29/08 ,  H03K3/02 ,  H03K3/37 ,  H03K17/284 ,  H03L7/00 ,  G01K7/183 ,  G01K7/20 ,  G01R19/2506 ,  G05F1/648 ,  G11C7/02 ,  G11C7/1039 ,  G11C7/14 ,  G11C7/20 ,  H03K17/223 ,  H03K17/24 ,  H03K5/1252 ,  H03K5/153 ,  H03K5/19 ,  H03K5/2472

Abstract: A system and method for protecting against a voltage glitch are provided. Generally, the system includes a reset-detector coupled to a supply voltage (VCC) and to a power-on-reset (POR) block, and a glitch-detector coupled to VCC and the reset-detector. The reset-detector is operable to provide a signal to the POR block to generate a global- reset-signal when VCC decreases below a minimum and remains low for at least a first time. The glitch-detector is operable to provide a glitch-signal to the reset-detector to cause it to provide the signal to the POR block when VCC decreases below the minimum and remains low for at least a second time, where the second time is less than the first. The reset-detector can further include a retention-circuit operable to recall a glitch-signal was received and signal the POR block when VCC is restored. Other embodiments are also disclosed.

公开(公告)号：WO2021219419A1

公开(公告)日：2021-11-04

申请号：PCT/EP2021/060087

申请日：2021-04-19

Applicant: AMS INTERNATIONAL AG

Inventor： LEONARDO, Vincenzo

IPC: H03K17/14 ,  H03K17/22 ,  H03K17/567

Abstract: A power on reset circuit comprises terminals (101, 102) for reference and supply potentials (VSS, VDD) and a voltage divider (130) coupled therebetween. First and second transistors (110, 120) of a bandgap circuit are resistively coupled to the reference potential terminal (101) and have bases connected to the voltage divider (130). Current mirrors (150, 160, 170) couple the collectors of the first and second transistors (110, 120) to an output terminal (103) providing an output signal (POR) indicating a power on reset condition. A first compensation transistor (180) is coupled between the collector of one of the transistors (120) and the reference potential terminal (101), and a second compensation transistor (190) is coupled between the output terminal (103) and the reference potential terminal (101) to compensate the effect of parasitic substrate currents in response to an external interference.

公开(公告)号：WO2021159526A1

公开(公告)日：2021-08-19

申请号：PCT/CN2020/075421

申请日：2020-02-14

Applicant: 华为技术有限公司

Inventor： 赵鹏飞 ,  谭丽娟

IPC: H03K17/22 ,  H02J7/00

Abstract: 一种集成电路、控制方法及系统，用以提高集成电路的可靠性。其中，集成电路主要包括电源管脚（P1）、配置管脚（P4，P5）、上拉开关电阻（KR1，KR2）和控制单元（2011），该集成电路能够通过其配置管脚（P4，P5）为目标芯片（202）提供控制信号。在集成电路中，上拉开关电阻（KR1，KR2）的第一端与电源管脚（P1）连接，上拉开关电阻（KR1，KR2）的第二端与配置管脚（P4，P5）连接，上拉开关电阻（KR1，KR2）的控制端与控制单元（2011）连接；电源管脚（P1）可以接收集成电路的供电电压；控制单元（2011）可以在目标芯片（202）上电之前，控制上拉开关电阻（KR1，KR2）处于断开状态。有利于防止目标芯片（202）在上电之前从集成电路的配置管脚（P4，P5）接收到误差信号，从而有利于提高集成电路的可靠性。此外，还有利于简化集成电路的外围电路的结构。

公开(公告)号：WO2021119578A1

公开(公告)日：2021-06-17

申请号：PCT/US2020/064786

申请日：2020-12-14

Applicant: TEXAS INSTRUMENTS INCORPORATED ,  TEXAS INSTRUMENTS JAPAN LIMITED

Inventor： KAUR, Divya ,  CHAUHAN, Rajat

IPC: H03K17/22 ,  G11C5/14

Abstract: A power-on-reset (POR) circuit (800) includes an NFET branch (302) and a PFET branch (306). The NFET branch (302) includes: an n-channel field effect transistor (NFET) (310, 312) having a first threshold voltage (Vthn); and a first quiescent bias current source (304) coupled between a supply terminal (VDD) and the NFET (310, 312). The PFET branch (306) includes: a p-channel field effect transistor (PFET) (316, 318) having a second threshold voltage (Vthp); and a second quiescent bias current source (308) coupled between a ground terminal and the PFET (316, 318). The POR circuit (800) is configured to provide a POR signal at an output terminal (816, 818, 820) based on: the first threshold voltage (Vthn) or the second threshold voltage (Vthp), whichever is larger; and a voltage margin (Vmargin). The output terminal (816) is coupled between the PFET branch (306) and the second quiescent bias current source (308).

公开(公告)号：WO2021075150A1

公开(公告)日：2021-04-22

申请号：PCT/JP2020/031733

申请日：2020-08-21

Applicant: 富士電機株式会社

Inventor： 赤羽　正志

IPC: H03K3/037 ,  H03K17/16 ,  H03K17/22

Abstract: 簡単な構成で、電源電圧が変動した場合においても、回路の誤動作を防止することが可能なフィルタ回路及び半導体装置を提供する。ラッチ回路と、立ち上がり調整部とを備える。ラッチ回路は、第１入力端子に入力されるセット信号と第２入力端子に入力されるリセット信号をそれぞれラッチする。立ち上がり調整部は、電源投入時のセット信号またはリセット信号の立ち上がり時間を、ラッチ回路の前段に配置される時定数回路で規定される時間より短くする。

公开(公告)号：WO2020018681A1

公开(公告)日：2020-01-23

申请号：PCT/US2019/042227

申请日：2019-07-17

Applicant: TEXAS INSTRUMENTS INCORPORATED ,  TEXAS INSTRUMENTS JAPAN LIMITED

Inventor： KAUR, Divya ,  CHAUHAN, Rajat ,  SINGHAL, Vipul, Kumar

IPC: H03K17/22

Abstract: In a circuit (100), an input stage (110) includes a first transistor device (114) configured to generate a first output signal (116) in response to a first bias current (118) activating the first transistor device (114) by exceeding a first threshold voltage of the first transistor device (114). A compensation stage (130) includes a second transistor device (134) coupled with a third transistor device (138). The second transistor device (134) is activated in response to the first output signal (116) exceeding a second threshold voltage of the second transistor device (134). The third transistor device (138) is activated in response to activation of the second transistor device (134) and a second bias current (140). The compensation stage (130) is configured to generate a second output signal (150) in response to the activation of the third transistor device (138). An output stage (160) is configured to generate a reset signal (164) in response to the second output signal (150) exceeding a third threshold voltage.

公开(公告)号：WO2019007394A1

公开(公告)日：2019-01-10

申请号：PCT/CN2018/094647

申请日：2018-07-05

Applicant: 中兴通讯股份有限公司

Inventor： 何健

IPC: H03K17/22

CPC classification number: H03K17/22

Abstract: 按键消抖方法及装置、包含机械键的设备、及存储介质。所述按键消抖方法包括步骤：检测机械键所在的电路产生的按键信号（110）；当检测到所述按键信号时，计时器复位并开始计时（120）；判断计时器的计时时间是否达到预设的时间阈值（130）；以及如果所述计时器的计时时间达到预设的时间阈值，准备检测机械键所在的电路产生的下一按键信号（140）。

公开(公告)号：WO2018073029A1

公开(公告)日：2018-04-26

申请号：PCT/EP2017/075589

申请日：2017-10-09

Applicant: ROBERT BOSCH GMBH

Inventor： TZIVANOPOULOS, Chrysanthos ,  KAISER, Thomas

IPC: H03K17/0412 ,  H03K17/284 ,  H03K17/691 ,  H03K17/687 ,  H03K17/22 ,  H03K17/06

Abstract: Die vorliegende Erfindung betrifft eine Schaltungsanordnung zum Schalten eines Hochvolt-MOSFETs (7) zur Vorladung einer Zwischenkreis-Kapazität eines Hochvolt-Bordnetzes mit einer ersten Schaltungsbaugruppe (11) mittels welcher die Schaltzeiten eines zum Laden der Zwischenkreiskapazitat verwendeten Hochvolt-MOSFETs verringert werden können.

Abstract translation:

本发明涉及一种电路用于预充电的中间电路电容＆AUML（7）的开关的高电压MOSFET;借助于高电压车辆电气系统的吨与第一电路组件（11），其中的一个用于充电的开关时间 直流链路电容使用高压MOSFET可以减少。