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    EMBEDDED RING OSCILLATOR NETWORK FOR INTEGRATED CIRCUIT SECURITY AND THREAT DETECTION
    2.
    发明申请
    EMBEDDED RING OSCILLATOR NETWORK FOR INTEGRATED CIRCUIT SECURITY AND THREAT DETECTION 审中-公开
    嵌入式环振荡器网络，用于集成电路安全和威胁检测

    公开(公告)号：WO2012122309A3

    公开(公告)日：2012-12-27

    申请号：PCT/US2012028134

    申请日：2012-03-07

    Applicant: UNIV CONNECTICUT ,  TEHRANIPOOR MOHAMMAD ,  WANG XIAOXIAO ,  ZHANG XUEHUI

    Inventor： TEHRANIPOOR MOHAMMAD ,  WANG XIAOXIAO ,  ZHANG XUEHUI

    IPC: H03K3/027

    CPC classification number: H03K3/0315 ,  G09C1/00 ,  H03K3/0322 ,  H03L7/0995 ,  H04L9/0662 ,  H04L9/3278 ,  H04L2209/12

    Abstract: Aspects of the disclosure relate to combining on-chip structure with external current measurements for threat detection in an integrated circuit. This method considers Trojans' impact on neighboring cells and on the entire IC's power consumption, and effectively localizes the measurement of dynamic power. An on-chip structure can permit threat detections. In one aspect, the on-chip structure can comprise a plurality of sensors distributed across the entirety of the IC, with each sensor of the plurality of sensors being placed in different rows of a standard-cell design. In another aspect, data analysis can permit separating effect of process variations on transient power usage of the IC from effects of a hardware threat such power usage. The on-chip structure also can be employed for implementation of a PE-PUF.

    Abstract translation: 本公开的方面涉及将集成电路中的片上结构与用于威胁检测的外部电流测量结合在一起。 这种方法考虑到木马对周边小区的影响和整个IC的功耗，并有效地定位了动态功率的测量。 片上结构可以允许威胁检测。 在一个方面，片上结构可以包括分布在整个IC整体上的多个传感器，多个传感器的每个传感器被放置在标准单元设计的不同行中。 在另一方面，数据分析可以允许过程变化对IC的瞬态功率使用的分离效应与硬件威胁的影响的这种功率使用的影响。 片上结构也可用于实现PE-PUF。

    比較回路、半導体装置
    3.
    发明申请
    比較回路、半導体装置 审中-公开

    公开(公告)号：WO2021111772A1

    公开(公告)日：2021-06-10

    申请号：PCT/JP2020/040385

    申请日：2020-10-28

    Applicant: 富士電機株式会社

    Inventor： 赤羽　正志

    IPC: H03K3/027 ,  H03K3/353 ,  H03K17/687 ,  H03K5/08

    Abstract: 比較回路は、入力電圧が、第１しきい値電圧を上回ると、第１論理レベルの出力電圧を出力し、前記入力電圧が、前記第１しきい値電圧より低い第２しきい値電圧を下回ると、第２論理レベルの前記出力電圧を出力する、比較回路であって、前記入力電圧を、第１電圧と、前記第１電圧より低い第２電圧と、に変換する変換回路と、前記第１電圧が、第３しきい値電圧を上回ると、前記第１論理レベルの前記出力電圧を出力し、前記第２電圧が、前記第３しきい値電圧より低い第４しきい値電圧を下回ると、前記第２論理レベルの前記出力電圧を出力する論理回路と、を備える。

    NEGATIVE EDGE FLIP-FLOP WITH DUAL-PORT SLAVE LATCH
    4.
    发明申请
    NEGATIVE EDGE FLIP-FLOP WITH DUAL-PORT SLAVE LATCH 审中-公开
    双口边缘双面双面双面拉链

    公开(公告)号：WO2014124037A1

    公开(公告)日：2014-08-14

    申请号：PCT/US2014/014919

    申请日：2014-02-05

    Applicant: TEXAS INSTRUMENTS INCORPORATED ,  TEXAS INSTRUMENTS JAPAN LIMITED

    Inventor： BARTLING, Steven ,  KHANNA, Sudhanshu

    IPC: H03K3/027 ,  H03K3/356

    CPC classification number: H03K3/012 ,  H03K3/289 ,  H03K3/35625

    Abstract: In an embodiment of the invention, a flip-flop circuit (100) contains a 2-input multiplexer (102), a master latch (104), a transfer gate (106) and a slave latch (108). The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch. The clock signals CLK and CLKN and retention control signals RET and RETN determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D2, the clock signals CLK and CLN, the retain control signals RET and RETN, the slave control signals SS and SSN. The signals CLK, CLKN, RET, RETN, SS and SSN determine whether the output of the master latch or the second data bit D2 is latched in the slave latch. Control signals RET and RETN determine when data is stored in the slave latch during retention mode.

    Abstract translation: 在本发明的实施例中，触发器电路（100）包含2输入多路复用器（102），主锁存器（104），传输门（106）和从锁存器（108）。 复用器的扫描使能控制信号SE和SEN确定数据还是扫描数据被输入到主锁存器。 时钟信号CLK和CLKN以及保持控制信号RET和RETN确定主锁存器何时被锁存。 从锁存器被配置为接收主锁存器的输出，第二数据位D2，时钟信号CLK和CLN，保持控制信号RET和RETN，从控制信号SS和SSN。 信号CLK，CLKN，RET，RETN，SS和SSN确定主锁存器或第二数据位D2的输出是否锁存在从锁存器中。 在保持模式期间，控制信号RET和RETN确定数据是否存储在从锁存器中。

    EMBEDDED RING OSCILLATOR NETWORK FOR INTEGRATED CIRCUIT SECURITY AND THREAT DETECTION
    6.
    发明申请
    EMBEDDED RING OSCILLATOR NETWORK FOR INTEGRATED CIRCUIT SECURITY AND THREAT DETECTION 审中-公开
    嵌入式环形振荡器网络，用于集成电路安全和威胁检测

    公开(公告)号：WO2012122309A2

    公开(公告)日：2012-09-13

    申请号：PCT/US2012/028134

    申请日：2012-03-07

    Applicant: UNIVERSITY OF CONNECTICUT ,  TEHRANIPOOR, Mohammad ,  WANG, Xiaoxiao ,  ZHANG, Xuehui

    Inventor： TEHRANIPOOR, Mohammad ,  WANG, Xiaoxiao ,  ZHANG, Xuehui

    IPC: H03K3/027

    CPC classification number: H03K3/0315 ,  G09C1/00 ,  H03K3/0322 ,  H03L7/0995 ,  H04L9/0662 ,  H04L9/3278 ,  H04L2209/12

    Abstract: Aspects of the disclosure relate to combining on-chip structure with external current measurements for threat detection in an integrated circuit. This method considers Trojans' impact on neighboring cells and on the entire IC's power consumption, and effectively localizes the measurement of dynamic power. An on-chip structure can permit threat detections. In one aspect, the on-chip structure can comprise a plurality of sensors distributed across the entirety of the IC, with each sensor of the plurality of sensors being placed in different rows of a standard-cell design. In another aspect, data analysis can permit separating effect of process variations on transient power usage of the IC from effects of a hardware threat such power usage. The on-chip structure also can be employed for implementation of a PE-PUF.

    Abstract translation: 本公开的各方面涉及将集成电路中的片上结构与用于威胁检测的外部电流测量进行组合。 这种方法考虑了木马对邻近单元和整个IC功耗的影响，并有效地定位了动态功耗的测量。 片上结构可以允许威胁检测。 在一个方面，芯片上结构可以包括跨整个IC分布的多个传感器，多个传感器中的每个传感器被放置在标准单元设计的不同行中。 在另一方面，数据分析可以允许IC的瞬态功率使用中的工艺变化与诸如功率使用的硬件威胁的影响相分离。 片上结构也可用于实现PE-PUF。

    多安定回路
    7.
    发明申请
    多安定回路 审中-公开
    多电平电路

    公开(公告)号：WO2003028214A1

    公开(公告)日：2003-04-03

    申请号：PCT/JP2001/008121

    申请日：2001-09-19

    Applicant: 鈴木利康

    Inventor： 鈴木利康

    IPC: H03K3/027

    CPC classification number: H03K3/3565 ,  H03K3/038 ,  H03K3/3568

    Abstract: A multi−stable circuit capable of outputting a voltage or potential depending on its stable state and used for a multivalue memory cell, a multivalue memory, multivalue storage means, a multivalue logic circuit, a multivalue computer, multivalue control means, and so on. For example, in the case of a 10−stable circuit, the potential rises gradually from a power line (V1) to a power line (V10), "pull−down means having negative resistance characteristics" is connected between the power line (V1) and an input/output terminal (Tio), "bi−directional pull means bi−directionally having the negative resistance characteristics" is connected between each of the power lines (V2) to (V9) and the input/output terminal (Tio), and "pull−up means having the negative resistance characteristics" is connected between the power line (V10) and the input/output terminal (Tio). The negative resistance characteristics are the "negative resistance characteristics in which the resistance decreases as the terminal voltage decreases and in which the resistance increases as the terminal voltage increases". The use of eight bi−directional pull means shortens the reading time while eliminating unfeasible read, transition of the stable state in reading, and any read error.

    Abstract translation: 能够根据其稳定状态输出电压或电位并用于多值存储单元，多值存储器，多值存储装置，多值逻辑电路，多值计算机，多值控制装置等的多稳态电路。 例如，在10稳定电路的情况下，电位从电力线（V1）向电力线（V10）逐渐上升，“负电阻特性的下拉装置”连接在电力线（V1 ）和输入输出端子（Tio）之间，连接在每个电源线（V2）至（V9）和输入/输出端子（Tio）之间的“具有负电阻特性的双向拉力装置” ，并且在电力线（V10）和输入输出端子（Tio）之间连接“具有负电阻特性的上拉装置”。 负电阻特性是“端电压降低时电阻下降，电阻随着端电压上升而电阻上升的负电阻特性”。 使用八个双向拉取装置缩短读取时间，同时消除不可读的读取，读取中稳定状态的转换以及任何读取错误。

    CLOCKLESS PROGRAMMABLE PULSE WIDTH GENERATION USING AN INVERSE CHAOTIC MAP
    8.
    发明申请
    CLOCKLESS PROGRAMMABLE PULSE WIDTH GENERATION USING AN INVERSE CHAOTIC MAP 审中-公开

    公开(公告)号：WO2019237114A1

    公开(公告)日：2019-12-12

    申请号：PCT/US2019/036371

    申请日：2019-06-10

    Applicant: COHEN, Seth, D.

    Inventor： COHEN, Seth, D.

    IPC: H03K3/00 ,  H03K3/02 ,  H03K3/027 ,  H03K3/84 ,  H03K5/01 ,  H03K5/08 ,  H03K5/13 ,  H03K7/08

    Abstract: Technologies are provided for generation of programmable pulse signals using inverse chaotic maps, without reliance on a clocking signal. Some embodiments of the technologies include an apparatus that can receive a sequence of bits having a defined number of bits, where the sequence of bits represent a desired continuous pulse signal having a programmable width in time-domain. The apparatus can also can receive a precursor continuous pulse signal having an arbitrary width in time-domain that fits within the dynamic range of the apparatus. The apparatus can generate the desired continuous pulse signal by transforming the precursor continuous pulse signal using the sequence of bits and an inverse chaotic map.

    INTEGRATED CIRCUITRY FOR GENERATING A CLOCK SIGNAL IN AN IMPLANTABLE MEDICAL DEVICE
    9.
    发明申请
    INTEGRATED CIRCUITRY FOR GENERATING A CLOCK SIGNAL IN AN IMPLANTABLE MEDICAL DEVICE 审中-公开
    用于在可植入医疗器械中产生时钟信号的集成电路

    公开(公告)号：WO2014143206A1

    公开(公告)日：2014-09-18

    申请号：PCT/US2013/069900

    申请日：2013-11-13

    Applicant: BOSTON SCIENTIFIC NEUROMDULATION CORPORATION

    Inventor： FELDMAN, Emanuel ,  MARNFELDT, Goran, N. ,  PARRAMON, Jordi

    IPC: A61N1/05 ,  A61N1/36 ,  H03K3/011 ,  H03K3/027

    CPC classification number: H03K3/03 ,  A61N1/0526 ,  A61N1/0551 ,  A61N1/36125 ,  H03K3/011 ,  H03K3/027

    Abstract: Timer circuitry completely formable in an integrated circuit (IC) for generating a clock signal in an implantable medical device is disclosed. The timer circuitry can be formed on the same Application Specific Integrated Circuit typically used in the implant, and requires no external components. The timer circuitry comprises modification to a traditional astable timer circuit. A resistance in the disclosed timer circuit can be trimmed to adjust the frequency of the clock signal produced, thus allowing that frequency to be set to a precise value during manufacturing. Precision components are not needed in the RC circuit, which instead are used to set the rough value of the frequency of the clock signal. A regulator produces a power supply for the timer circuitry from a main power supply (Vcc), producing a clock signal with a frequency that is generally independent of temperature and Vcc fluctuations.

    Abstract translation: 公开了在用于在可植入医疗装置中产生时钟信号的集成电路（IC）中完全形成的定时器电路。 定时器电路可以形成在通常用于植入物的相同的专用集成电路上，并且不需要外部组件。 定时器电路包括对传统的不稳定定时器电路的修改。 所公开的定时器电路中的电阻可以被修整以调整产生的时钟信号的频率，从而允许在制造期间将该频率设置为精确的值。 RC电路中不需要精密元件，而是用来设置时钟信号频率的粗略值。 调节器从主电源（Vcc）为定时器电路产生电源，产生具有通常与温度和Vcc波动无关的频率的时钟信号。

    POSITIVE EDGE PRESET RESET FLIP-FLOP WITH DUAL-PORT SLAVE LATCH
    10.
    发明申请
    POSITIVE EDGE PRESET RESET FLIP-FLOP WITH DUAL-PORT SLAVE LATCH 审中-公开
    正向边缘预置位复位带双口自动锁定的浮动片

    公开(公告)号：WO2014130561A1

    公开(公告)日：2014-08-28

    申请号：PCT/US2014/017176

    申请日：2014-02-19

    Applicant: TEXAS INSTRUMENTS INCORPORATED ,  TEXAS INSTRUMENTS JAPAN LIMITED

    Inventor： BARTLING, Steven ,  KHANNA, Sudhanshu

    IPC: H03K3/027 ,  H03K3/356

    CPC classification number: H03K3/35625 ,  G11C11/419

    Abstract: In an embodiment, a flip-flop circuit contains a 2-input multiplexer (102), a master latch 9104), a transfer gate (106) and a slave latch (108). The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch. Clock signals CKT and CLKZ and retention control signals RET and RETN determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D2, the clock signals CKT and CLN, the retain control signals RET and RETN, the slave control signals SS and SSN. The signals CKT, CLKZ, RET, RETN, SS, SSN and PREN determine whether the output of the master latch or the second data bit D2 is latched in the slave latch. Control signals RET and RETN determine when data is stored in the slave latch during retention mode.

    Abstract translation: 在一个实施例中，触发器电路包含2输入多路复用器（102），主锁存器9104），传输门（106）和从锁存器（108）。 复用器的扫描使能控制信号SE和SEN确定数据还是扫描数据被输入到主锁存器。 时钟信号CKT和CLKZ以及保持控制信号RET和RETN确定主锁存器何时被锁存。 从锁存器被配置为接收主锁存器的输出，第二数据位D2，时钟信号CKT和CLN，保持控制信号RET和RETN，从控制信号SS和SSN。 信号CKT，CLKZ，RET，RETN，SS，SSN和PREN确定主锁存器或第二数据位D2的输出是否锁存在从锁存器中。 在保持模式期间，控制信号RET和RETN确定数据是否存储在从锁存器中。

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