US09287559B2
A lithium secondary battery comprising a positive electrode, a negative electrode, a separator inserted between the positive electrode and the negative electrode and a non-aqueous electrolyte is provided. The positive electrode comprises a first positive electrode active material represented by following Chemical Formula 1. And the non-aqueous electrolyte comprises a first lithium salt, a second lithium salt represented by following Chemical Formula 2 and a non-aqueous organic solvent. LixMyOz [Chemical Formula 1] Li+RCOO− [Chemical Formula 2] (In Chemical Formulae 1 and 2, M=NiaMnbCoc, in which 0
US09287558B2
The invention relates to lithium-bearing iron phosphate in the form of micrometric mixed aggregates of nanometric particles, to an electrode and cell resulting therefrom and to the method for manufacturing same, which is characterized by a nanomilling step.
US09287557B2
When an active material with low ionic conductivity and low electric conductivity is used in a nonaqueous electrolyte secondary battery such as a lithium ion battery, it is necessary to reduce the sizes of particles; however, reduction in sizes of particles leads to a decrease in electrode density. Active material particles of an oxide, which include a transition metal and have an average size of 5 nm to 50 nm, are mixed with an electrolyte, a binder, and the like to form a slurry, and the slurry is applied to a collector. Then, the collector coated with the slurry is exposed to a magnetic field. Accordingly, the active material particles aggregate so that the density thereof increases. Alternatively, the active material particles may be applied to the collector in a magnetic field. The use of the aggregating active material particles makes it possible to increase the electrode density.
US09287555B2
Disclosed are mixed metal oxidized hydroxide precursors that can be used for the preparation of lithium mixed metal oxide cathode materials for secondary lithium ion batteries and methods of making such mixed metal precursors. The precursors typically are particles of nickel, cobalt, and manganese mixed metal oxidized hydroxides with varying metal molar ratios prepared in co-precipitation reactions in two sequential reactors.
US09287548B2
A terminal unit of a secondary battery and a method of manufacturing the same, the terminal unit including an electrode rivet, the electrode rivet being connected to an electrode assembly; a rivet terminal, the rivet terminal including a metal different from a metal of the electrode rivet; and a medium plate, the medium plate including a same metal as the electrode rivet, and being disposed between the electrode rivet and the rivet terminal so as to be overlap-weldable to the rivet terminal.
US09287547B2
In one embodiment, an electrochemical system includes an interconnector busbar including a substrate and a coating contacting the substrate, the coating including a layer of electroplated elemental nickel.
US09287546B2
The present invention relates to a galvanic element, in particular an element of the button cell type, which has a long service life even when there are high mechanical or thermal loads. The element has a cathode, an anode, an electrolyte, a separator arranged between the anode and cathode, and a housing, which comprises a housing cup, a housing cover and a sealing element, the sealing element insulating the housing cup against the housing cover. According to the invention, the sealing element is rigidly connected to the separator.
US09287542B2
A multi-layer, microporous polyolefin membrane comprising first microporous layers constituting at least both surface layers, and at least one second microporous layer disposed between both surface layers, the first microporous layer comprising a first polyethylene resin containing 8% or more by mass of ultra-high-molecular-weight polyethylene having a weight-average molecular weight of 1×106 or more, the second microporous layer comprising a second polyethylene resin containing 7% or less by mass of the ultra-high-molecular-weight polyethylene, and having a structure in which a pore diameter distribution curve obtained by mercury intrusion porosimetry has at least two peaks, and the total thickness of the first microporous layers being 15-60% per 100% of the total thickness of the first and second microporous layers.
US09287535B2
A secondary battery, which has no raw material injection spot and a burr on a lower surface of the insulating member. The sidewalls are formed on the opposite side to the side on which bending stress is applied, and the sidewalls act as a structural resistor, which result in preventing the plate from bending. The insulating member inserted into the container has an inversely stepped part to keep the insulating member from escaping from the container. A fabrication method of the secondary battery whereby an insulating member is prepared by inserting a raw material from the side on which the sidewall is to be formed into a mold and solidifying the inserted raw material, the insulating member is positioned over the electrode assembly inserted into a container, and a cap is coupled to an opening of the container with the insulating member positioned over the electrode assembly.
US09287534B2
A rechargeable battery includes an electrode assembly including first electrodes and second electrodes, a casing including a space in which the electrode assembly is embedded, a cap plate combined with the casing, and a first thin film insulating member fused with the casing and surrounding the casing.
US09287529B2
A method for fabricating the OLED including a color conversion layer using roll-to-roll processing is provided. To elaborate, the method for fabricating an OLED comprising: bonding an OLED and an inorganic phosphor to each other through roll-to-roll processing is provided, wherein the inorganic phosphor is provided as a color conversion layer.
US09287521B2
A transparent electrode is provided with a nitrogen-containing layer, an electrode layer having silver as the main component thereof, and an aluminum intermediate layer, wherein the aluminum intermediate layer is in contact with the nitrogen-containing layer and the electrode layer and sandwiched between the nitrogen-containing layer and the electrode layer. The nitrogen-containing layer is formed by using a compound containing a nitrogen atom. The effective unshared electron pair content [n/M] of this compound satisfies “3.9×10−3≦[n/M]”, where n is the number of unshared electron pair(s) not involved in aromaticity and not coordinated to metal, among unshared electron pair(s) owned by the nitrogen atom, and M is molecular weight.
US09287505B2
The invention relates to novel polymers containing repeating units based on thieno[3,4-b]thiophene, monomers and methods for their preparation, their use as semiconductors in organic electronic (OE) devices, especially in organic photovoltaic (OPV) devices, and to OE and OPV devices comprising these polymers.
US09287497B2
Integrated circuits with a Hall effect sensor and methods for fabricating such integrated circuits are provided. The method includes forming a buried plate layer within a substrate and overlying a substrate base, where the buried plate layer is doped with an “N” type dopant. A cover insulating layer if formed overlying the buried plate layer, and a plurality of contact points are formed adjacent to the cover insulating layer.
US09287493B2
A storage element including a storage layer configured to hold information by use of a magnetization state of a magnetic material, with a pinned magnetization layer being provided on one side of the storage layer, with a tunnel insulation layer, and with the direction of magnetization of the storage layer being changed through injection of spin polarized electrons by passing a current in the lamination direction, so as to record information in the storage layer, wherein a spin barrier layer configured to restrain diffusion of the spin polarized electrons is provided on the side, opposite to the pinned magnetization layer, of the storage layer; and the spin barrier layer includes at least one material selected from the group composing of oxides, nitrides, and fluorides.
US09287492B2
A piezoelectric polymer element such as a fiber or film is described, having a solid cross-section and a substantially homogeneous composition. A method of forming such a piezoelectric polymer element is also described. The method has the steps of extruding a polymer material and concurrently poling a region of the extruded material. Apparatus for forming such a piezoelectric polymer element is also described that comprises an extruder for extruding a polymer element from a granular feed and a pair of electrodes for applying an electric field across a region of the element concurrently with its extrusion. Also described is a piezoelectric construct having such piezoelectric polymer elements interposed between two conductive layers. A system for converting mechanical energy into electrical energy is described in which each of the piezoelectric construct's two conductive layers is connected to a respective terminal of a rectifying circuit.
US09287491B2
A piezoelectric element 300 includes a first electrode 60, a piezoelectric layer 70 arranged on the first electrode 60, and a second electrode 80 arranged on the piezoelectric layer 70, in which the piezoelectric layer 70 includes a composite oxide which has a perovskite structure and the composite oxide has a composition represented as a mixed crystal of bismuth ferrate and strontium titanate.
US09287490B2
A laminated piezoelectric element that includes a piezoelectric element layer and a matching layer. The piezoelectric element layer is configured to have a plurality of piezoelectric layers and a plurality of electrode layers laminated together. The matching layer is laminated on the piezoelectric element layer, and is different in acoustic impedance from the piezoelectric element layer. When Vp represents the acoustic velocity in the piezoelectric element layer, Vm represents the acoustic velocity in the matching layer, Tp represents the thickness dimension of the piezoelectric element layer, and Tm represents the thickness dimension of the matching layer, Vp/Vm=Tp/Tm holds. Further, when W represents the dimension of the laminated piezoelectric element in the width direction, Tp+Tm>W holds.
US09287484B2
A thermoelectric material including: a two dimensional nanostructure having a core and a shell on the core. Also, a thermoelectric element and a thermoelectric apparatus including the thermoelectric material, and a method of preparing the thermoelectric material.
US09287473B2
The present invention relates to an epoxy resin composition for an optical semiconductor device having an optical semiconductor element mounting region and having a reflector that surrounds at least a part of the region, the epoxy resin composition being an epoxy resin composition for forming the reflector, the epoxy resin composition including the following ingredients (A) to (E): (A) an epoxy resin; (B) a curing agent; (C) a white pigment; (D) an inorganic filler; and (E) a specific release agent.
US09287464B2
A light-emitting element includes a light-emitting layer, and an optical function film. The light-emitting layer is configured to include a first plane with a first electrode, a second plane with a second electrode, and a circumferential plane connecting the first and second planes, the second plane being opposing to the first plane, and the light-emitting layer being made of a semiconductor. The optical function film is configured to include a reflection layer being able to reflect light coming from the light-emitting layer, the reflection layer being provided with first and second regions, the first region covering the second plane and the circumferential plane, the second region protruding from the first region to an outside of the light-emitting layer to expose an end plane thereof.
US09287456B2
Provided is an element structure whereby it is possible to produce a silicon-germanium light-emitting element enclosing an injected carrier within a light-emitting region. Also provided is a method of manufacturing the structure. Between the light-emitting region and an electrode there is produced a narrow passage for the carrier, specifically, a one-dimensional or two-dimensional quantum confinement region. A band gap opens up in this section due to the quantum confinement, thereby forming an energy barrier for both electrons and positive holes, and affording an effect analogous to a double hetero structure in an ordinary Group III-V semiconductor laser. Because no chemical elements other than those used in ordinary silicon processes are employed, the element can be manufactured inexpensively, simply by controlling the shape of the element.
US09287455B2
A carbon doped short period superlattice is provided. A heterostructure includes a short period superlattice comprising a plurality of quantum wells alternating with a plurality of barriers. One or more of the quantum wells and/or the barriers includes a carbon doped layer (e.g., a non-percolated or percolated carbon atomic plane).
US09287453B2
In the case that a functional layer, made of a nitride of a group 13 element, is formed on a composite substrate including a sapphire body and a gallium nitride crystal layer disposed over the sapphire body, the deviation of the function is prevented. The composite substrate 4 includes a sapphire body 1A and a gallium nitride crystal layer 3 disposed over the sapphire body. Aa warpage of the composite substrate is in a range of not less than +40 μm and not more than +80 μm per 5.08 cm in length.
US09287446B2
A nanostructure semiconductor light emitting device includes a base layer, an insulating layer, a plurality of light emitting nanostructures, and a contact electrode. The base layer is formed of a first conductivity-type semiconductor material. The insulating layer is disposed on the base layer. Each light emitting nanostructure is disposed in a respective opening of a plurality of openings in the base layer, and includes a nanocore formed of the first conductivity-type semiconductor material, and an active layer and a second conductivity-type semiconductor layer sequentially disposed on a surface of the nanocore. The contact electrode is spaced apart from the insulating layer and is disposed on a portion of the second conductivity-type semiconductor layer. A tip portion of the light emitting nanostructure has crystal planes different from those on side surfaces of the light emitting nanostructure.
US09287442B2
A solution for designing and/or fabricating a structure including a quantum well and an adjacent barrier is provided. A target band discontinuity between the quantum well and the adjacent barrier is selected to coincide with an activation energy of a dopant for the quantum well and/or barrier. For example, a target valence band discontinuity can be selected such that a dopant energy level of a dopant in the adjacent barrier coincides with a valence energy band edge for the quantum well and/or a ground state energy for free carriers in a valence energy band for the quantum well. Additionally, a target doping level for the quantum well and/or adjacent barrier can be selected to facilitate a real space transfer of holes across the barrier. The quantum well and the adjacent barrier can be formed such that the actual band discontinuity and/or actual doping level(s) correspond to the relevant target(s).
US09287431B2
Voltage-matched thin film multijunction solar cell and methods of producing cells having upper CdTe pn junction layers formed on a transparent substrate which in the completed device is operatively positioned in a superstate configuration. The solar cell also includes a lower pn junction formed independently of the CdTe pn junction and an insulating layer between CdTe and lower pn junctions. The voltage-matched thin film multijunction solar cells further include a parallel connection between the CdTe pn junction and lower pn junctions to form a two-terminal photonic device. Methods of fabricating devices from independently produced upper CdTe junction layers and lower junction layers are also disclosed.
US09287426B1
Techniques for epitaxial growth of CZT(S,Se) materials on Si are provided. In one aspect, a method of forming an epitaxial kesterite material is provided which includes the steps of: selecting a Si substrate based on a crystallographic orientation of the Si substrate; forming an epitaxial oxide interlayer on the Si substrate to enhance wettability of the epitaxial kesterite material on the Si substrate, wherein the epitaxial oxide interlayer is formed from a material that is lattice-matched to Si; and forming the epitaxial kesterite material on a side of the epitaxial oxide interlayer opposite the Si substrate, wherein the epitaxial kesterite material includes Cu, Zn, Sn, and at least one of S and Se, and wherein a crystallographic orientation of the epitaxial kesterite material is based on the crystallographic orientation of the Si substrate. A method of forming an epitaxial kesterite-based photovoltaic device and an epitaxial kesterite-based device are also provided.
US09287424B2
Disclosed are a method of forming a back reflection layer in a solar cell, a composition used therefor, and a solar cell having a back reflection layer formed by the method, which layer has superior heat-resistance and various types of durabilities, and can contribute to improving the conversion rate of solar cells and reliability during long-term use, and which method can form a back reflection layer in a solar cell easily and at low cost. The polyimide resin composition for use in forming a back reflection layer in a solar cell includes an organic solvent, a polyimide resin dissolved in the organic solvent, and light-reflecting particles dispersed in the organic solvent.
US09287419B2
This invention is related to novel perylene diester derivatives represented by the general formula (I) or general formula (II) as described herein. The derivatives are useful in various applications, such as luminescent dyes for optical light collection systems, fluorescence-based solar collectors, fluorescence-activated displays, and/or single-molecule spectroscopy. The invention also relates to a luminescent medium, such as a luminescent film, that can significantly enhance the solar harvesting efficiency of thin film CdS/CdTe or CIGS solar cells. The luminescent medium comprises an optically transparent polymer matrix and at least one luminescent dye that comprises a perylene diester derivative. Over 16% of an efficiency enhancement to a CdS/CdTe solar cell and over 12% of an efficiency enhancement to a CIGS solar cell can be achieved.
US09287417B2
Disclosed herein is a semiconductor chip package, which includes a semiconductor chip, a plurality of vias, an isolation layer, a redistribution layer, and a packaging layer. The vias extend from the lower surface to the upper surface of the semiconductor chip. The vias include at least one first via and at least one second via. The isolation layer also extends from the lower surface to the upper surface of the semiconductor chip, and part of the isolation layer is disposed in the vias. The sidewall of the first via is totally covered by the isolation layer while the sidewall of the second via is partially covered by the isolation layer. The redistribution layer is disposed below the isolation layer and fills the plurality of vias, and the packaging layer is disposed below the isolation layer.
US09287416B2
A semiconductor system of a Schottky diode is described having an integrated PN diode as a clamping element, which is suitable in particular as a Zener diode having a breakdown voltage of approximately 20 V for use in motor vehicle generator systems. The semiconductor system of the Schottky diode includes a combination of a Schottky diode and a PN diode. The breakdown voltage of the PN diode is much lower than the breakdown voltage of the Schottky diode, the semiconductor system being able to be operated using high currents during breakdown operation.
US09287412B2
This invention describes a field-effect transistor in which the channel is formed in an array of quantum dots. In one embodiment the quantum dots are cladded with a thin layer serving as an energy barrier. The quantum dot channel (QDC) may consist of one or more layers of cladded dots. These dots are realized on a single or polycrystalline substrate. When QDC FETs are realized on polycrystalline or nanocrystalline thin films they may yield higher mobility than in conventional nano- or microcrystalline thin films. These FETs can be used as thin film transistors (TFTs) in a variety of applications. In another embodiment QDC-FETs are combined with: (a) coupled quantum well SWS channels, (b) quantum dot gate 3-state like FETs, and (c) quantum dot gate nonvolatile memories.
US09287410B2
A semiconductor device with favorable electrical characteristics is provided. The semiconductor device includes an insulating layer, a semiconductor layer over the insulating layer, a source electrode layer and a drain electrode layer electrically connected to the semiconductor layer, a gate insulating film over the semiconductor layer, the source electrode layer, and the drain electrode layer, and a gate electrode layer overlapping with part of the semiconductor layer, part of the source electrode layer, and part of the drain electrode layer with the gate insulating film therebetween. A cross section of the semiconductor layer in the channel width direction is substantially triangular or substantially trapezoidal. The effective channel width is shorter than that for a rectangular cross section.
US09287409B2
One object of the present invention is to provide a structure of a transistor including an oxide semiconductor in a channel formation region in which the threshold voltage of electric characteristics of the transistor can be positive, which is a so-called normally-off switching element, and a manufacturing method thereof. A second oxide semiconductor layer which has greater electron affinity and a smaller energy gap than a first oxide semiconductor layer is formed over the first oxide semiconductor layer. Further, a third oxide semiconductor layer is formed to cover side surfaces and a top surface of the second oxide semiconductor layer, that is, the third oxide semiconductor layer covers the second oxide semiconductor layer.
US09287408B2
Provided is a field-effect transistor (FET) having small off-state current, which is used in a miniaturized semiconductor integrated circuit. The field-effect transistor includes a thin oxide semiconductor which is formed substantially perpendicular to an insulating surface and has a thickness of greater than or equal to 1 nm and less than or equal to 30 nm, a gate insulating film formed to cover the oxide semiconductor, and a strip-like gate which is formed to cover the gate insulating film and has a width of greater than or equal to 10 nm and less than or equal to 100 nm. In this structure, three surfaces of the thin oxide semiconductor are covered with the gate, so that electrons injected from a source or a drain can be effectively removed, and most of the space between the source and the drain can be a depletion region; thus, off-state current can be reduced.
US09287406B2
A dual-mode transistor structure comprises a semiconductor body. The semiconductor body of the device includes a channel region, a p-type terminal region (operable as a source or drain) adjacent a first side of the channel region and an n-type terminal region (operable as a source or drain) adjacent a second side of the channel region. A gate insulator is disposed on a surface of the semiconductor body over the channel region. A gate is disposed on the gate insulator over the channel region. A first assist gate is disposed on a first side of the gate, and a second assist gate is disposed on a second side of the gate. Optionally, a back gate can be included beneath the channel region. Biasing the assist gates can be used to select n-channel or p-channel modes in a single device.
US09287404B2
A method of manufacturing a semiconductor device includes providing dielectric stripe structures extending from a first surface into a semiconductor substrate between semiconductor fins. A first mask is provided that covers a first area including first stripe sections of the dielectric stripe structures and first fin sections of the semiconductor fins. The first mask exposes a second area including second stripe and second fin sections. A channel/body zone is formed in the second fin sections by introducing impurities, wherein the first mask is used as an implant mask. Using an etch mask that is based on the first mask, recess grooves are formed at least in the second stripe sections.
US09287403B1
A method for manufacturing a FinFET, and FinFETs are provided. In various embodiments, the method for manufacturing a FinFET includes forming a fin structure over a substrate. Next, a dummy gate is deposited across over the fin structure. The method continues with forming a pair of first spacers on sidewalls of the dummy gate. Then, a source/drain region is formed in the fin structure not covered by the dummy gate. The method further includes removing the dummy gate to expose the fin structure. After that, the first spacers are truncated, and a gate stack is formed to cover the exposed fin structure and top surfaces of the first spacers.
US09287399B2
A faceted intrinsic buffer semiconductor material is deposited on sidewalls of a source trench and a drain trench by selective epitaxy. A facet adjoins each edge at which an outer sidewall of a gate spacer adjoins a sidewall of the source trench or the drain trench. A doped semiconductor material is subsequently deposited to fill the source trench and the drain trench. The doped semiconductor material can be deposited such that the facets of the intrinsic buffer semiconductor material are extended and inner sidewalls of the deposited doped semiconductor material merges in each of the source trench and the drain trench. The doped semiconductor material can subsequently grow upward. Faceted intrinsic buffer semiconductor material portions allow greater outdiffusion of dopants near faceted corners while suppressing diffusion of dopants in regions of uniform width, thereby suppressing short channel effects.
US09287383B2
A method for manufacturing a semiconductor device includes providing a semiconductor substrate having first and second sides, laterally spaced semiconductor devices integrated into the semiconductor substrate, and a drift region of a first conductivity type. Trenches are formed in the semiconductor substrate at the first side of the semiconductor substrate between laterally adjacent semiconductor devices, each of the trenches having two sidewalls and a bottom. First doping zones of a second conductivity type are formed in the semiconductor substrate at least along the sidewalls of the trenches. The first doping zones form pn-junctions with the drift region. Second doping zones of the first conductivity type are formed in the semiconductor substrate at least along a part of the bottom of the trenches. The second doping zones adjoin the drift region. The semiconductor substrate is cut along the second doping zones in the trenches to separate the semiconductor devices.
US09287380B2
A method of manufacturing a semiconductor device and a novel semiconductor device are disclosed herein. An exemplary method includes sputtering a capping layer in-situ on a gate dielectric layer, before any high temperature processing steps are performed.
US09287368B2
According to one embodiment, a nitride semiconductor device includes a substrate; semiconductor stacked layers including a nitride semiconductor provided on the substrate, and having a buffer layer, a carrier running layer provided on the buffer layer, and a barrier layer provided on the carrier running layer; a source electrode and a drain electrode provided on the semiconductor stacked layers and in contact with the semiconductor stacked layers; and a gate electrode provided on the semiconductor stacked layers and provided between the source electrode and the drain electrode.The gate electrode has a stacked structure, and a gate metal layer, a barrier metal layer, a first interconnection layer, and a second interconnection layer including Al are sequentially stacked from a side of a surface of the semiconductor stacked layers in the stacked structure.
US09287367B2
Disclosed are semiconductor devices and methods of manufacturing the same. The semiconductor device includes: a first conductive type semiconductor layer including a first lower conductive type semiconductor layer and a first upper conductive type semiconductor layer; a V-pit passing through at least one portion of the first upper conductive type semiconductor layer; a second conductive type semiconductor layer placed over the first conductive type semiconductor and filling the V-pit; and an active layer interposed between the first and second conductive type semiconductor layers with the V-pit passing through the active layer. The first upper conductive type semiconductor layer has a higher defect density than the first lower conductive type semiconductor layer and includes a V-pit generation layer comprising a starting point of the V-pit. The semiconductor device includes the V-pits having a large size and a high density to efficiently preventing damage to the semiconductor device due to electrostatic discharge.
US09287365B2
A semiconductor device includes a semiconductor layer, an insulating film of silicon nitride on the semiconductor layer, source and drain electrodes formed in openings of the insulating film and in contact with the semiconductor layer, and a gate electrode formed in an opening in the insulating film that is located between the source electrode and the drain electrode and formed in contact with the semiconductor layer. The insulating film has an Si content that is uniform in a direction of thickness of the insulating film, an upper region, and a lower region. The upper region can have an oxygen concentration that is greater than that of the lower region. The upper region can be formed by exposing the surface of the insulating film to ozone or an oxygen plasma.
US09287363B2
A method of manufacturing a semiconductor device may include: preparing a substrate formed of SiC; depositing crystalline or amorphous silicon (Si) on one surface of the substrate to form a first semiconductor layer; and performing a heat treatment under a nitrogen atmosphere to form a second semiconductor layer formed of SiCN between the substrate and the first semiconductor layer.
US09287357B2
An integrated circuit may include multiple first, non-Si, nanosheet field-effect transistors (FETs) and multiple second, Si, nanosheet FETs. Nanosheets of ones of the first, non-Si, nanosheet FETs may include less than about 30% Si. The first, non-Si, nanosheet FETs may define a critical speed path of the circuit of the integrated circuit. Nanosheets of ones of the second, Si, nanosheet FETs may include more than about 30% Si. The second, Si, nanosheet FETs may define a non-critical speed path of the integrated circuit. Ones of the first, non-Si, nanosheet FETs may be configured to have a higher speed than a speed of ones of the second, Si, nanosheet FETs.
US09287355B2
A semiconductor device comprises a semiconductor substrate; an element-forming region that includes semiconductor elements formed on the semiconductor substrate; a buried electrode plug formed so as to penetrate through the semiconductor substrate; and a trench-type electrode that is buried in a trench within the semiconductor substrate positioned between the element-forming region and the buried electrode plug.
US09287352B2
To provide a crystalline oxide semiconductor film, an ion is made to collide with a target including a crystalline In—Ga—Zn oxide, thereby separating a flat-plate-like In—Ga—Zn oxide in which a first layer including a gallium atom, a zinc atom, and an oxygen atom, a second layer including an indium atom and an oxygen atom, and a third layer including a gallium atom, a zinc atom, and an oxygen atom are stacked in this order; and the flat-plate-like In—Ga—Zn oxide is irregularly deposited over a substrate while the crystallinity is maintained.
US09287344B2
Providing for a monolithic magnetic induction device having low DC resistance and small surface area is described herein. By way of example, the magnetic induction device can comprise a substrate (e.g., a semiconductor substrate) having trenches formed in a bottom layer of the substrate, and holes formed in the substrate between the trenches and an upper layer of the substrate. Additionally, the magnetic induction device can comprise a conductive coil embedded or deposited within the trenches. The magnetic induction device can further comprise a set of conductive vias formed in the holes that electrically connect the bottom layer of the substrate with the upper layer. Further, one or more integrated circuit components, such as active devices, can be formed in the upper layer, at least in part above the conductive coil. The vias can be utilized to connect to integrated circuit components with the conductive coil, where suitable.
US09287339B2
An organic light emitting display and a method of manufacturing the same. The organic light-emitting display is a transparent display where one can see through the display to view an image on the other side of the display. Each pixel of the display has a first region that includes an organic light emitting diode and a thin film transistor, and a larger second region that is transparent. The second region is made of either transparent layers or ultra thin layers so that light is not blocked. A second electrode of the display may include magnesium and may be produced by a selective deposition process, so that use of a fine metal mask may be avoided.
US09287337B2
A first substrate provided with a plurality of pixel electrodes is prepared. A bank layer is formed so as to be placed on the periphery of each pixel electrode to define a plurality of pixel regions and contain a metal ion adsorbent. An organic electro-luminescence film is formed so as to be placed on the bank layer and the plurality of pixel electrodes and contain a metal complex which is a compound having a ligand coordinated to a metal ion. A common electrode is formed on the organic electro-luminescence film. The organic electro-luminescence film is formed such that the concentration of the metal ions is decreased above the bank layer by the metal ion adsorbent.
US09287334B2
An organic light emitting diode display includes a display panel including a display area to which a touch screen panel is attached and a pad area in which a metal wire is formed; a cover window on one side of the display panel; a resin layer between the display panel and the cover window; and a touch screen circuit film in the pad area and connected to the touch screen panel, at least one of the touch screen circuit film and the metal wire including an ultraviolet ray transmitter configured to increase a hardening degree of the resin layer in the pad area.
US09287325B2
A vertical type semiconductor device and a fabrication method thereof are provided. The vertical type semiconductor device includes a pillar structure having a stacking structure of a conductive layer and a data storage material and formed on a common source region, and a gate electrode formed to surround the data storage material of the pillar structure.
US09287324B2
A non-volatile memory includes a substrate, a fin structure, a gate structure, a transition layer, and a metal layer. The fin structure is protruded from the substrate. A first source/drain region and a second source/drain region are formed in the fin structure. The gate structure covers a top surface and two lateral surfaces of a part of the fin structure. The gate structure is arranged between the first source/drain region and the second source/drain region. The transition layer is in contact with the second source/drain region. The metal layer is in contact with the transition layer. By setting or resetting the transition layer, a resistance value of the transition layer is correspondingly changed.
US09287322B2
A method for providing a magnetic junction usable in a magnetic device and the magnetic junction are described. The method includes providing a reference layer, a nonmagnetic spacer layer and a free layer. The nonmagnetic spacer layer is between the free and reference layers. An interface is between the nonmagnetic spacer and free layers. Providing the free layer further includes applying at least one electric field while the free layer is at a local temperature above an operating temperature of the magnetic junction. The electric field(s) exert a force on an anion in the free layer in a direction away from the interface between the free layer and the nonmagnetic spacer layer. The magnetic junction is configured such that the free layer is switchable between stable magnetic states when a write current is passed through the magnetic junction.
US09287319B2
A CMOS multi-pinned pixel having very low dark current and very high charge transfer performance over that of conventional CMOS pixels is disclosed. The CMOS pixel includes epitaxial silicon and at least one transfer gate formed upon the epitaxial silicon. A pinned-photodiode is formed in the epitaxial silicon. A multi-pinned (MP) implant layer is implanted in the epitaxial silicon at least partially extending across the pinned-photodiode and substantially underlying the at least one transfer gate of the CMOS pixel to promote dark current passivation during an accumulation state and promote charge transfer during a transfer state.
US09287313B2
An integrated circuit having an array of APS cells. Each cell in the array has at least one transistor source or drain region that is raised relative to a channel region formed in a semiconductor substrate. The raised source or drain region includes doped polysilicon deposited on the surface of the semiconductor body and a region of the bodyextending to the channel region that has been doped to an opposite doping type from that of the channel region by diffusion of dopants from the deposited polysilicon.
US09287295B2
A display apparatus is disclosed. The apparatus includes a plurality of unit pixels each comprising a plurality of sub pixels, a plurality of scan wires, and a plurality of scan lines branching off from each of the scan wires and extending in a first direction. The number of scan lines from each scan wire equals the number of sub pixels for each pixel, and each scan line connects one of the scan wires with one of the sub pixels of each of a plurality of unit pixels. The apparatus also includes a plurality of data lines extending in a second direction orthogonal to the first direction and which are connected to the plurality of sub pixels. The apparatus also includes a first power supply line extending in the second direction and connected to the sub pixels, and a plurality of test pads, each connected to the scan lines of one of the scan wires.
US09287292B2
To provide a semiconductor device having a thin-film BOX-SOI structure and capable of realizing a high-speed operation of a logic circuit and a stable operation of a memory circuit. A semiconductor device according to the present invention includes a semiconductor support substrate, an insulation layer having a thickness of at mast 10 nm, and a semiconductor layer. In an upper surface of the semiconductor layer, a first field-effect transistor including a first gate electrode and constituting a logic circuit is formed. Further, in the upper surface of the semiconductor layer, a second field-effect transistor including a second gate electrode and constituting a memory circuit is formed. At least three well regions having different conductivity types are formed in the semiconductor support substrate. In the presence of the well regions, a region of the semiconductor support substrate below the first gate electrode and a region of the semiconductor support substrate below the second gate electrode are electrically separated from each other.
US09287290B1
Disclosed herein are 3D NAND memory devices having vertical NAND strings with a crystalline silicon channel and techniques for fabricating the same. The NAND string channel may be a single crystal of silicon or have a few large grains of polysilicon. The single crystal may have a (100) orientation with respect to a tunnel oxide of the 3D NAND string. When the channel region comprises grains of polysilicon, predominantly all of the silicon channel is part of a grain of polysilicon having the (100) orientation. The (100) orientation may be favorable for high carrier mobility. Techniques using metal induced crystallization (MIC) for forming the NAND strings having a crystalline silicon channel are also disclosed.
US09287287B2
Present example embodiments relate generally to methods of fabricating a semiconductor device, and semiconductor devices thereof, comprising providing a substrate, forming an insulating base layer on the substrate, and disposing a conductive layer on the insulating base layer at an initial temperature. The methods further comprise increasing the initial temperature at a first increase rate to a first increased temperature and performing an in-situ annealing process to the conductive layer at the first increased temperature. The methods further comprise increasing the first increased temperature at a second increase rate to a second increased temperature, and forming an insulating layer after performing the in-situ annealing process at the second increased temperature.
US09287284B2
Semiconductor device formed by a first conductive strip of semiconductor material; a control gate region of semiconductor material, facing a channel portion of the first conductive strip, and an insulation region arranged between the first conductive strip and the control gate region. The first conductive strip includes a conduction line having a first conductivity type and a control line having a second conductivity type, arranged adjacent and in electrical contact with each other, and the conduction line forms the channel portion, a first conduction portion and a second conduction portion arranged on opposite sides of the channel portion.
US09287281B2
Flash devices and methods of manufacturing the same are provided. The device may include: a semiconductor substrate, with a well region therein; a sandwich arrangement on the well region, including a back gate conductor, semiconductor fins on opposite sides of the back gate conductor, and back gate dielectric layers separating the back gate conductor from the respective semiconductor fins, wherein the well region serves as a part of a conductive path to the back gate conductor; a front gate stack intersecting the semiconductor fins, including a floating gate dielectric layer, a floating gate conductor, a control gate dielectric layer, and a control gate conductor stacked sequentially, wherein the floating gate dielectric layer separates the floating gate conductor from the semiconductor fins; an insulating cap on top of the back gate conductor and the semiconductor fins to separate the back gate conductor from the front gate stack; and source and drain regions connected to a channel region provided by each of the semiconductor fins. The device can achieve high integration and low power consumption.
US09287272B2
A high-k dielectric metal trench capacitor and improved isolation and methods of manufacturing the same is provided. The method includes forming at least one deep trench in a substrate, and filling the deep trench with sacrificial fill material and a poly material. The method further includes continuing with CMOS processes, comprising forming at least one transistor and back end of line (BEOL) layer. The method further includes removing the sacrificial fill material from the deep trenches to expose sidewalls, and forming a capacitor plate on the exposed sidewalls of the deep trench. The method further includes lining the capacitor plate with a high-k dielectric material and filling remaining portions of the deep trench with a metal material, over the high-k dielectric material. The method further includes providing a passivation layer on the deep trench filled with the metal material and the high-k dielectric material.
US09287267B2
A highly integrated DRAM is provided. A bit line is formed over a first insulator, a second insulator is formed over the bit line, third insulators which are in a stripe shape and the like are formed over the second insulator, and a semiconductor region and a gate insulator are formed to cover one of the third insulators. The bit line is connected to the semiconductor region through first contact plugs. Then, a conductive film is formed and subjected to anisotropic etching to form word lines at side surfaces of the third insulators, and a second contact plug is formed to be connected to a capacitor at a top of the one of the third insulators. By synchronizing the word lines, electric charge is accumulated or released through the capacitor. With such a structure, the area of a memory cell can be 4F2.
US09287265B2
A semiconductor device includes a substrate with an active region defined by a device isolation layer. A word line extends over the active region in a first direction, and a plurality of interconnections extends over the word line in a second direction perpendicular to the first direction. A contact pad is disposed between and spaced apart from the word line and the plurality of interconnections, extending in the first direction to overlap the plurality of interconnections and the active region when viewed from a plan view. A lower contact plug electrically connects the contact pad to the active region. An upper contact plug electrically connects the contact pad to one of the plurality of interconnections.
US09287262B2
A fin field effect transistor (FinFET), and a method of forming, is provided. The FinFET has a fin having one or more semiconductor layers epitaxially grown on a substrate. A first passivation layer is formed over the fins, and isolation regions are formed between the fins. An upper portion of the fins are reshaped and a second passivation layer is formed over the reshaped portion. Thereafter, a gate structure may be formed over the fins and source/drain regions may be formed.
US09287256B2
Provided is a semiconductor device including a substrate of a first conductivity type, a first circuit region, a separation region, a second circuit region, and a rectifying element. The rectifying element has a second conductivity type layer, a first high concentration second conductivity type region, a second high concentration second conductivity type region, an element isolation film, a first insulation layer, and a first conductive film. A first contact is coupled to the first high concentration second conductivity type region, and a second contact is coupled to the second high concentration second conductivity type region. A third contact is coupled to the first conductive film. The first contact, the second contact and the third contact are separated from each other.
US09287253B2
In one well bias arrangement, no well bias voltage is applied to the n-well, and no well bias voltage is applied to the p-well. Because no external well bias voltage is applied, the n-well and the p-well are floating, even during operation of the devices in the n-well and the p-well. In another well bias arrangement, the lowest available voltage is not applied to the p-well, such as a ground voltage, or the voltage applied to the n+-doped source region of the n-type transistor in the p-well. This occurs even during operation of the n-type transistor in the p-well. In yet another well bias arrangement, the highest available voltage is not applied to the n-well, such as a supply voltage, or the voltage applied to the p+-doped source region of the p-type transistor in the n-well. This occurs even during operation of the p-type transistor in the n-well.
US09287245B2
A contoured package on package joint and a method for making the same are disclosed herein. A method for forming a device comprises providing a substrate having a package land and forming a mounting stud on the package land. A molded underfill is applied to the substrate and in contact with the mounting stud. A contoured stud surface is formed on the mounting stud is contoured and connecting member attached to the contoured stud surface with a second package attached to the connecting member. The connecting member may be solder and have a spherical shape. The contoured stud surface may be etched or mechanically formed to have a hemispherical shape conforming to the connecting member shape.
US09287243B2
The present invention relates to an optical device and a method for manufacturing the same. The technical object of the invention is to realize a surface emitting body which allows heat generated from a light-emitting chip to be easily dissipated, eliminates the need for an additional wiring layer, and allows a singular light emitting chips or a plurality of light emitting chips to be arranged in series, in parallel, or in series-parallel. The present invention discloses an optical device comprising: a substrate; a plurality of light emitting chips disposed on the substrate; a plurality of conductive wires which electrically connect the substrate with the light emitting chips such that the plurality of light emitting chips are connected to each other in series, in parallel or in series-parallel; and a protective layer which covers the plurality of light emitting chips and the plurality of conductive wires on the substrate.
US09287241B2
The present invention provides a light emitting device which comprises blue and red light emitting diode (LED) chips and at least one phosphor for emitting green light by means of light emitted from the blue LED chip, and an LCD backlight including the light emitting device. According to the light emitting device of the present invention, uniform white light can be implemented and both high luminance and wider color reproduction range can also be obtained. Accordingly, an LCD backlight for uniform light distribution on an LCD as well as low power consumption and high durability can be manufactured using the light emitting device.
US09287234B2
A device includes a metal pad over a substrate. A passivation layer includes a portion over the metal pad. A post-passivation interconnect (PPI) is electrically coupled to the metal pad, wherein the PPI comprises a portion over the metal pad and the passivation layer. A polymer layer is over the PPI. A dummy bump is over the polymer layer, wherein the dummy bump is electrically insulated from conductive features underlying the polymer layer.
US09287228B2
A method of etching a semiconductor structure, comprises contacting an under bump metallization (UBM) with an etching composition. The UBM includes an underlying layer comprising titanium and an overlying layer comprising a second metal. The etching composition is a liquid comprising at least 0.1 wt % hydrofluoric acid and at least 0.1 wt % phosphoric acid.
US09287226B2
To reduce the radio frequency (RF) losses associated with high RF loss plating, such as, for example, Nickel/Palladium/Gold (Ni/Pd/Au) plating, an on-die passive device, such as a capacitor, resistor, or inductor, associated with a radio frequency integrated circuit (RFIC) is placed in an RF upper signal path with respect to the RF signal output of the RFIC. By placing the on-die passive device in the RF upper signal path, the RF current does not directly pass through the high RF loss plating material of the passive device bonding pad.
US09287225B2
A method of manufacturing a semiconductor device includes forming an opening in a first substrate and filling the opening with a metal to form a first connection electrode. The first substrate is then polished by chemical mechanical polishing under conditions such that a polishing rate of the metal is less that of the region surrounding the metal. The chemical mechanical polishing thereby causes the first connection electrode to protrude from the surface of the first substrate. The first substrate is stacked with a second substrate having a second connection electrode. The first and second connection electrodes are bonded by applying pressure and heating to a temperature that is below the melting point of the metal of the first connection electrode.
US09287222B1
An integrated semiconductor device and method for fabricating the same are provided wherein the integrated semiconductor device comprises a substrate a first stress-inducing layer, a second stress-inducing layer and an integrated circuit layer. The first stress-inducing layer covers on the substrate. The second stress-inducing layer partially covers on the first stress-inducing layer. The integrated circuit layer is bonded over the substrate.
US09287220B2
Disclosed herein is a semiconductor package. The semiconductor package according to a preferred embodiment of the present invention includes: a first substrate having an electronic device mounted on both surfaces thereof; and a second substrate bonded to one surface of the first substrate and including an insertion part in which the electronic device mounted on one surface of the first substrate is inserted, wherein the second substrate includes a ground and a shielding wall which is formed along an inner wall or an outer wall of the second substrate.
US09287215B2
A source driver integrated circuit comprises a common node; a plurality of pads for inputting power, a portion of which are connected to an external power source and the remainder of which are connected to the portion through the common node; and a common power line which is connected to the plurality of power input pads through the common node. As a result, the resolution of adjacent channels varies very little and block dimming between channels can be resolved.
US09287209B2
Embodiments described herein provide a structure for finger capacitors, and more specifically metal-oxide-metal (“MOM”) finger capacitors and arrays of finger capacitors. A plurality of Shallow Trench Isolation (STI) formations is associated with every other column of capacitor fingers, with poly fill formations covering the STI formations to provide a more robust and efficient structure.
US09287193B2
A semiconductor device 1 includes a thermal radiation member 4; a first semiconductor chip 21 connected to the thermal radiation member 4; a second semiconductor chip 22 connected to the thermal radiation member 4; and sealing resin 93 sealing the first semiconductor chip 21 and the second semiconductor chip 22. The semiconductor device 1 comprises a first thermal diffusion member 31 connected to the thermal radiation member 4; a second thermal diffusion member 32 connected to the thermal radiation member 4; and a cooler 5 configured to cool the first thermal diffusion member 31 and the second thermal diffusion member 32. A space between the first thermal diffusion member 31 and the second thermal diffusion member 32 is positioned to oppose a space between the first semiconductor chip 21 and the second semiconductor chip 22 via the thermal radiation member 4.
US09287191B2
An embodiment is a structure. The structure comprises a substrate, a chip, and a reinforcement component. The substrate has a first surface, and the first surface comprises depressions. The chip is over and attached to the first surface of the substrate. The reinforcement component is over a first area of the first surface of the substrate. The first area is not under the chip. The reinforcement component has a portion disposed in at least some of the depressions in the first area.
US09287189B2
Methods, systems, and apparatuses for semiconductor devices are provided herein. A semiconductor device includes an array of conductive pads for signals. One or more non-linear compliant springs may be present to route signals from the conductive pads to interconnect pads formed on the semiconductor device to attach bump interconnects. Each non-linear compliant spring may include one or more routing segments. The semiconductor device may be mounted to a circuit board by the bump interconnects. When the semiconductor device operates, heat may be generated by the semiconductor device, causing thermal expansion by the semiconductor device and the circuit board. The semiconductor device and circuit board may expand by different amounts due to differences in their thermal coefficients of expansion. The non-linear compliant springs provide for compliance between the conductive pads and bump interconnects to allow for the different rates of expansion.
US09287188B2
A wafer seal ring may be formed on a first and/or a second wafer. One or both of the first and/or second wafers may have one or more dies formed thereon. The wafer seal ring may be formed to surround the dies of a corresponding wafer. One or more die seal rings may be formed around the one or more dies. The wafer seal ring may be formed to a height that may be approximately equal to a height of one or more die seal rings formed on the first and/or second wafer. The wafer seal ring may be formed to provide for eutectic or fusion bonding processes. The first and second wafers may be bonded together to form a seal ring structure between the first and second wafers. The seal ring structure may provide a hermetic seal between the first and second wafers.
US09287183B1
A method for detecting contamination on a patterned substrate includes: performing a via etch operation on a substrate, wherein the via etch operation is configured to define a via feature on the substrate and expose an etch-stop layer at a bottom of the via feature; performing an etch-stop removal operation on the substrate, wherein the etch-stop removal operation is configured for removing the etch-stop layer at the bottom of the via feature to expose a metallic feature underlying the etch-stop layer; applying an electroless deposition solution to the substrate, the applied electroless deposition solution configured for selectively depositing a metallic material over the exposed metallic feature and on metallic contaminants on exposed surfaces of the substrate, the metallic contaminants being generated from the metallic feature during the etch-stop removal operation; performing an inspection operation on the substrate to identify the metallic contaminants that have been deposited with the metallic material.
US09287181B2
Provided is a method for fabricating a semiconductor device. The method includes forming an interlayer insulating layer on a substrate, the interlayer insulating layer including a first trench; forming a high-k dielectric layer in the first trench; successively forming a diffusion layer and a blocking layer on the high-k dielectric layer; subsequently performing annealing; after the annealing, successively removing the blocking layer and the diffusion layer; forming a first barrier layer on the high-k dielectric layer; successively forming a work function adjustment layer and a gate conductor on the first barrier layer; and forming a capping layer on the gate conductor.
US09287179B2
The present disclosure involves a FinFET. The FinFET includes a fin structure formed over a substrate. A gate dielectric layer is least partially wrapped around a segment of the fin structure. The gate dielectric layer contains a high-k gate dielectric material. The FinFET includes a polysilicon layer conformally formed on the gate dielectric layer. The FinFET includes a metal gate electrode layer formed over the polysilicon layer. The present disclosure provides a method of fabricating a FinFET. The method includes providing a fin structure containing a semiconductor material. The method includes forming a gate dielectric layer over the fin structure, the gate dielectric layer being at least partially wrapped around the fin structure. The method includes forming a polysilicon layer over the gate dielectric layer, wherein the polysilicon layer is formed in a conformal manner. The method includes forming a dummy gate layer over the polysilicon layer.
US09287176B2
An optical device including a substrate formed of a light transmitting material and a light emitting layer formed on the front surface of the substrate. Both the front surface and the back surface of the substrate are parallel to each other and have substantially the same rectangular shape. The substrate has four side surfaces connecting the front surface and the back surface of the substrate. Each side surface of the substrate has a corrugated sectional shape such that a plurality of concave portions and convex portions are alternately formed.
US09287166B2
A system and a method for protecting vias is disclosed. An embodiment comprises forming an opening in a substrate. A barrier layer disposed in the opening including along the sidewalls of the opening. The barrier layer may include a metal component and an alloying material. A conductive material is formed on the barrier layer and fills the opening. The conductive material to form a via (e.g., TSV).
US09287165B2
A power semiconductor device includes a semiconductor body, having an active zone and a high voltage peripheral zone laterally adjacent to each other, the high voltage peripheral zone laterally surrounding the active zone. The device further includes a metallization layer on a front surface of the semiconductor body and connected to the active zone, a first barrier layer, comprising a high-melting metal or a high-melting alloy, between the active zone and the metallization layer, and a second barrier layer covering at least a part of the peripheral zone, the second barrier layer comprising an amorphous semi-isolating material. The first barrier layer and the second barrier layer partially overlap and form an overlap zone. The overlap zone extends over an entire circumference of the active zone. A method for producing such a power semiconductor device is also provided.
US09287162B2
A semiconductor structure is formed to include a non-conductive layer with at least one metal line, a first dielectric layer, a first stop layer, a second dielectric layer, a second stop layer, a third stop layer and a fourth stop layer. A first photoresist layer is formed over the upper stop layer to develop at least one via pattern. The structure is selectively etched to form the via pattern in the third stop layer through the fourth stop layer. The first photoresist layer is then removed. A second photoresist layer is formed over the upper stop layer to develop a plurality of trench patterns, each of the trench pattern comprising a via-trench portion in which the trench pattern is formed above the via pattern, and a trench portion that is remaining part of the trench pattern.
US09287161B2
A method of manufacturing a wiring includes sequentially forming a first insulation layer, a first layer, and a second layer on a substrate, etching an upper portion of the second layer a plurality of times to form a second layer pattern including a first recess having a shape of a staircase, etching a portion of the second layer pattern and a portion of the first layer under the first recess to form a first layer pattern including a second recess having a shape of a staircase similar to the first recess, etching a portion of the first layer pattern under the second recess to form a first opening exposing a portion of a top surface of the first insulation layer, etching the exposed portion of the first insulation layer to form a second opening through the first insulation layer, and forming a wiring filling the second opening.
US09287160B2
A semiconductor device, and a method of fabricating the same, include a substrate including two-dimensionally arranged active portions, device isolation patterns extending along sidewalls of the active portions, each of the device isolation patterns including first and second device isolation patterns, gate patterns extending across the active portions and the device isolation patterns, each of the gate patterns including a gate insulating layer, a gate line and a gate capping pattern, and ohmic patterns on the active portions, respectively. Top surfaces of the first device isolation pattern and the gate insulating layer may be lower than those of the second device isolation pattern and the gate capping pattern, respectively, and the ohmic patterns may include an extending portion on the first insulating layer.
US09287157B2
A semiconductor element that includes a forsy patterned conductive layer, a second pattern conductive layer and an insulating layer. The first surface of the second patterned conductive layer is connected to a second surface of the first patterned conductive layer. The insulating layer includes at least one space on a second surface thereof. The first patterned conductive layer and the second patterned conductive layer are embedded in the insulating layer between a first surface and a second surface thereof, the first surface of the first patterned conductive layer is entirely exposed on a first surface of the insulating layer, a second surface of the second patterned conductive layer is entirely exposed on the second surface of the insulating layer, and the space exposes the second surface of the first patterned conductive layer.
US09287146B2
To provide an induction heating apparatus that employs a batch-type heating system for heating a large-diameter wafer and can perform uniform heating with a high precision, an induction heating apparatus (10) that heats an inductive-heating target member using a magnetic flux generated from a solenoid-type induction heating coil (18) and heats a wafer (40) using the heat generated from the inductive-heating target member, wherein a plurality of inductive-heating target members 14 (14a, 14b, and 14c) of which principal surface is arranged perpendicularly to a core axis direction of the induction heating coil (18) are interspersed. In the induction heating apparatus (10) described above, a susceptor (12) may be configured by housing the inductive-heating target member (14) in a single holder (16) made of a member having magnetic permeability and heat conductivity.
US09287145B2
In a coating and developing treatment system including a treatment station and an interface station, the interface station has: a cleaning unit cleaning a rear surface of a wafer before the wafer is transferred into an exposure apparatus; an inspection unit inspecting whether the cleaned wafer is in an exposable state; and a wafer transfer mechanism including an arm transferring the wafer between the cleaning unit and the inspection unit. Each of the cleaning unit and the inspection unit is provided at multiple tiers in an up and down direction on the front side in the interface station, and the wafer transfer mechanism is provided in a region adjacent to the cleaning units and the inspection units.
US09287142B2
A management method is able to quickly investigate the cause of a defect generated in a semiconductor product manufacturing process. Manufacturing conditions in various QFP manufacturing steps are stored in a main server while correlating them with an identification number of the QFP, and a two-dimensional bar code corresponding to the identification number is stamped to the surface of the QFP. In the event of occurrence of a defect of the QFP, the manufacturing conditions for the QFP stored in the main server can be traced in an instant by reading the two-dimensional bar code of the QFP and thereby specifying the identification number.
US09287140B2
Provided are semiconductor packages having through electrodes and methods of fabricating the same. The method may include may include forming a wafer-level package including first semiconductor chips stacked on a second semiconductor chip, forming a chip-level package including fourth semiconductor chips stacked on a third semiconductor chip stacking a plurality of the chip-level packages on a back surface of the second semiconductor substrate of the wafer-level package, polishing the first mold layer of the wafer-level package and the first semiconductor chips to expose a first through electrodes of the first semiconductor chip, and forming outer electrodes on the polished first semiconductor chips to be connected to the first through electrodes, respectively.
US09287139B2
A method includes forming a dummy gate stack over a semiconductor substrate, removing the dummy gate stack to form a recess, and implanting a portion of the semiconductor substrate through the recess. During the implantation, an amorphous region is formed from the portion of the semiconductor substrate. The method further includes forming a strained capping layer, wherein the strained capping layer extends into the recess. An annealing is performed on the amorphous region to re-crystallize the amorphous region. The strained capping layer is then removed.
US09287137B2
Embodiments of the disclosure generally provide methods of forming a silicon containing layers in TFT devices. The silicon can be used to form the active channel in a LTPS TFT or be utilized as an element in a gate dielectric layer, a passivation layer or even an etch stop layer. The silicon containing layer is deposited by a vapor deposition process whereby an inert gas, such as argon, is introduced along with the silicon precursor. The inert gas functions to drive out weak, dangling silicon-hydrogen bonds or silicon-silicon bonds so that strong silicon-silicon or silicon-oxygen bonds remain to form a substantially hydrogen free silicon containing layer.
US09287136B2
Field effect transistors fabricated using atomic layer doping processes are disclosed. In accordance with an embodiment of an atomic layer doping method, a semiconducting surface and a dopant gas mixture are prepared. Further, a dopant layer is grown on the semiconducting surface by applying the dopant gas mixture to the semiconducting surface under a pressure that is less than 500 Torr and a temperature that is between 300° C. and 750° C. The dopant layer includes at least 4×1020 active dopant atoms per cm3 that react with atoms on the semiconducting surface such that the reacted atoms increase the conductivity of the semiconducting surface.
US09287133B2
A method for hard mask layer removal includes dispensing a chemical on a hard mask layer, in which the chemical includes an acidic chemical. The chemical is drained from a chamber after hard mask removal.
US09287131B2
A method involving identifying a pattern for an overall target cut mask to be used in patterning line-type features that includes a target non-rectangular opening feature having an inner, concave corner, decomposing the overall target cut mask pattern into first and second sub-target patterns, wherein the first sub-target pattern comprises a first rectangular-shaped opening feature corresponding to a first portion, but not all, of the target non-rectangular opening feature and the second sub-target pattern comprises a second rectangular-shaped opening feature corresponding to a second portion, but not all, of the target non-rectangular opening feature, the first and second openings overlapping adjacent the inner, concave corner, and generating first and second sets of mask data corresponding to the first and second sub-target patterns, wherein at least one of the first and second sets of mask data is generated based upon an identified contact-to-end-of-cut-line spacing rule.
US09287118B2
Provided is a highly integrated semiconductor device, a semiconductor device with large storage capacitance with respect to an area occupied by a capacitor, a semiconductor device capable of high-speed writing or reading, a semiconductor device with low power consumption, or a highly reliable semiconductor device. Provided are steps of forming a first oxide semiconductor over a first substrate, forming a first insulator over the first oxide semiconductor, injecting an ion into a region of the first oxide semiconductor through the first insulator, bonding a surface of the first insulator provided with the first substrate to a surface of a second insulator over a second substrate, performing a heat treatment in a state where the surfaces are bonded, separating the first substrate from the second substrate along the region of the first oxide semiconductor, and forming a second oxide semiconductor over the second substrate.
US09287117B2
To provide a highly reliable semiconductor device including an oxide semiconductor by suppression of change in its electrical characteristics. Oxygen is supplied from a base insulating layer provided below an oxide semiconductor layer and a gate insulating layer provided over the oxide semiconductor layer to a region where a channel is formed, whereby oxygen vacancies which might be generated in the channel are filled. Further, extraction of oxygen from the oxide semiconductor layer by a source electrode layer or a drain electrode layer in the vicinity of the channel formed in the oxide semiconductor layer is suppressed, whereby oxygen vacancies which might be generated in a channel are suppressed.
US09287115B2
A method of forming a semiconductor substrate including a type III-V semiconductor material directly on a dielectric material that includes forming a trench in a dielectric layer, and forming a via within the trench extending from a base of the trench to an exposed upper surface of an underlying semiconductor including substrate. A III-V semiconductor material is formed extending from the exposed upper surface of the semiconductor substrate filling at least a portion of the trench.
US09287111B2
An ozone gas generation processing apparatus that includes a light source of ultraviolet rays and a wafer placement section, generates ozone gas by irradiating ultraviolet rays from the light source in an atmosphere containing oxygen, and processes a wafer on the wafer placement section with the ozone gas, the ozone gas generation processing apparatus comprising a light-blocking plate that allows the generated ozone gas to pass therethrough and blocks the ultraviolet rays between the light source and the wafer placed on the wafer placement section. An ozone gas generation processing apparatus and a method of forming an oxide film silicon film can make an adjustment to make thinner an oxide film formed on a wafer surface, the wafer surface is not damaged by ultraviolet rays when processed, and a method for evaluating a silicon single crystal wafer, obtaining a more stable measurement value of C-V characteristics are provided.
US09287109B2
One method disclosed herein includes forming a layer of insulating material above a semiconductor substrate, forming a hard mask layer comprised of a metal-containing material above the layer of insulating material, forming a blanket protection layer on the hard mask layer, forming a masking layer above the protection layer, performing at least one etching process on the masking layer to form a patterned masking layer having an opening that stops on and exposes a portion of the blanket protection layer, confirming that the patterned masking layer is properly positioned relative to at least one underlying structure or layer and, after confirming that the patterned masking layer is properly positioned, performing at least one etching process through the patterned masking layer to pattern at least the blanket protection layer.
US09287097B2
The simulation method is for predicting a damage amount due to ultraviolet rays in manufacturing a semiconductor device. The method includes: calculating particle density by performing simulation based on a differential equation for the particle density; calculating emission intensity at each wavelength in a visible wavelength region based on the calculated particle density; obtaining an electron energy distribution function by comparing the calculated emission intensity at each wavelength in the visible wavelength region with an actually detected emission spectrum in the visible wavelength region with reference to information on emission species and an emission wavelength in a target manufacturing process; predicting an emission spectrum in an ultraviolet wavelength region by using the electron energy distribution function and a reaction cross-sectional area relating to the emission species; and predicting a damage amount due to the ultraviolet rays based on the predicted emission spectrum in the ultraviolet wavelength region.
US09287087B2
In a sample observation method, a sample stage is placed at a first tilt angle with respect to a charged particle beam, and an observation surface of a sample is irradiated with the charged particle beam to acquire a first charged particle image. The sample stage is then tilted to a second tilt angle different from the first tilt angle about a first sample stage axis, and the observation surface is again irradiated with the charged particle beam to acquire a second charged particle image. The sample stage is tilted to a tilt angle at which an area of the observation surface in the acquired charged particle image is the larger of the first charged particle image and the second charged particle image. The observation surface is then irradiated with the charged particle beam to observe the observation surface.
US09287085B2
A processing apparatus including a process chamber, a plasma source disposed within the process chamber, wherein the plasma source is movable in a first direction and is configured to emit an ion beam along a second direction that is orthogonal to the first direction. The apparatus may further include a platen disposed within the process chamber for supporting a substrate, and an ion beam current sensor that is disposed adjacent to the platen.
US09287080B2
A system and method for generating X-rays are provided. The X-ray source includes an X-ray chamber including a sidewall formed of a piezoelectric material at least partially surrounding an evacuated chamber, a cathode positioned at a first end of the evacuated chamber, an anode positioned at a second opposite end of the evacuated chamber, and a window positioned at the second end, the window substantially transparent to X-ray radiation. The window includes a target layer at least partially covering a surface of the window. The target layer is configured to receive a flow of electrons from the cathode and to generate a flow of X-rays from an interaction with the flow of electrons. The X-ray source includes an actuator coaxially aligned with the X-ray chamber and configured to generate a stress in the sidewall.
US09287077B2
A manufacturing method of a flexible display is provided, which comprises steps of forming an silicon layer on a rigid substrate, forming a frame-type silicon layer from the silicon layer, attaching a flexible substrate onto the surface of the rigid substrate on which the frame-type amorphous silicon layer is formed, forming a display film on the flexible substrate, and dehydrogenating the frame-type silicon layer after the formation of the display film is complete, so that the flexible substrate is separated from the frame-type silicon layer for obtaining the flexible display. The manufacturing method of the flexible display prevents the problem of low yield rate caused by the damage to the plastic substrate in the separation process.
US09287074B2
A relay for automatically selecting a monitoring range for monitoring a parameter of an input source and a method for monitoring a parameter of an input source can be provided whereby the relay comprises one or more terminals for coupling to the input source; a plurality of switchable circuits coupled to the one or more terminals; a processing module coupled to the plurality of switchable circuits for automatically selecting a monitoring range from a plurality of monitoring ranges based on a value of the parameter of the input source, each monitoring range associated with one or more of said switchable circuits; and a relay switch being configured to provide or disrupt electrical communication to a circuit, based on a trigger signal provided by the processing module. A signal conditioning module may also be provided for e.g. conditioning signals prior to selection of the monitoring range.
US09287068B2
A touch panel includes a protective cover with a lower surface herein, and an active region and a periphery region defined on the lower surface. A first sensing structure is disposed on the lower surface and covers the active region. A shelter layer is disposed on the lower surface and in the periphery region, wherein the shelter layer includes a highlight region and a highlight contrast region, a first pattern is disposed in the highlight region, and a non-transparent layer with a second pattern is disposed in the highlight region, wherein the first pattern is overlapped by the second pattern.
US09287067B2
Switch assembly for changing the direction of current from a power source to an appliance comprising—at least four wirings, two of the wirings are connectable with the power source and the remaining wirings are connectable with the appliance,—all wirings are fixed on the surface of a substrate and none of the wirings are directly connected to each other,—a first button comprising a first conductive pattern on one surface of said button,—a second button comprising a second conductive pattern on one surface of said button,—the surfaces of the buttons on which the conductive patterns are arranged face the surface of said substrate where the wirings are arranged,—the buttons are fixed on the substrate—the conductive patterns on the buttons and said wirings on the surface of the substrate are arranged in such a manner and said buttons are placed on said substrate in such manner, that (i) said conductive patterns on the buttons are not in contact with said wirings in an unpressed state of the buttons, (ii) one button connects by means of the conductive pattern in a pressed state simultaneously the first wiring of the two wirings with one wiring of the remaining wirings and the second wiring of the two wirings with another wiring of the remaining wirings to enable a first current path through the switch assembly, and (iii) the other button connects by means of the conductive pattern in a pressed state the first wiring of the two wirings with one wiring of the remaining wirings and the second wiring of the two wirings with another wiring of the remaining wirings to enable a second current path through the switch assembly being different to the first current path, wherein further the conductive patterns comprise a composition (CO) comprising a polymer and a conductive material dispersed in said polymer and/or a conjugated polymer.
US09287066B2
A key structure in an electronic product includes a housing. The key structure includes a pressing portion, a printed circuit board (PCB), a key, and a sensor. The key and the sensor are both located on the PCB and electronically connected with each other. When the pressing portion is pressed, the key structure acts as a mechanical key. When the pressing portion is simply touched, the key structure acts as a touch key.
US09287063B2
A bicycle handlebar system comprises a control element for controlling an electric auxiliary motor, said element being adapted to be fastened to the handlebar. The control element has a housing, wherein a plurality of switching elements is arranged in recesses in the housing, one membrane button is arranged in the housing per switching element, the switching element acting on said membrane button, and the membrane buttons are interconnected through a common flexibly conductor path.
US09287061B1
A rotor is shown for an electromechanical switching device, includes: a rotor housing; two contact bridges having in each case two contact portions; an intermediate element disposed between the two contact bridges and mounted so as to be rotatable about a rotation axis; and first spring pins and second spring pins; first spring elements and second spring elements. In an embodiment, the spring pins, the spring elements, and the intermediate element are operationally connected, and at least one of the first and second spring pins is disposed on the intermediate element and/or on the contact bridges such that the spring pin by rotating the rotor is tiltable between the two states in relation to the rotation axis. An embodiment furthermore relates to an electromechanical switching device including the rotor.
US09287060B2
In this device, a mechanism for receiving an input mechanical command and for actuating first and second switches comprises a lever having a first side arm tiltable about a swiveling axis of said lever and a second side arm tiltable about the same swiveling axis. The first side arm and the second side arm are respectively arranged on a first side and a second side opposite relative to said swiveling axis. The first side arm is an operating arm for operating the first switch. The second side arm is an operating arm for operating the second switch.
US09287053B2
A method of manufacturing a solid electrolytic capacitor having an even conductive polymer layer includes the steps of forming a conductive polymer layer on an anode element by bringing a dispersion containing a conductive solid and a first solvent into contact with the anode element having a dielectric film formed thereon, washing the anode element with a second solvent higher in boiling point than the first solvent, in which the conductive solid can be dispersed, after the conductive polymer layer is formed, and drying the anode element washed with the second solvent at a temperature not lower than the boiling point of the first solvent and lower than the boiling point of the second solvent.
US09287047B2
A multilayer ceramic capacitor may include: a ceramic body including a plurality of dielectric layers; a first capacitor part including a first internal electrode and a second internal electrode disposed in the ceramic body; second to fifth capacitor parts including a third internal electrode having first and second leads and a fourth internal electrode having third and fourth leads, the third and fourth internal electrodes being disposed on one dielectric layer in the ceramic body, and fifth and sixth internal electrodes disposed on another dielectric layer in the ceramic body; and a first external electrode and a second external electrode. The first capacitor part and the second to fifth capacitor parts may be connected in parallel to each other.
US09287044B2
There are provided an electronic component and a fabrication method thereof. The electronic component includes: a ceramic main body including end surfaces in a length direction, side surfaces in a width direction and top and bottom surfaces in a thickness direction; first and second external electrodes formed on the end surfaces, respectively; third and fourth external electrodes formed on the side surfaces, respectively; first internal electrodes formed within the ceramic main body and connected to first and second external electrodes; and second internal electrodes alternately arranged with the first internal electrodes, while having a ceramic layer interposed therebetween, and connected to the third and fourth external electrodes, wherein thickness t1 and t2 of the first and second internal electrodes is 0.9 μm or less, while a roughness R1 of the first internal electrode is lower than a roughness R2 of the second internal electrode.
US09287040B2
Systems and designs for tuning a wireless power transfer system are provided, which may include any number of features. In one embodiment, a wireless power transfer system can be configured such that resonant frequencies of the system move towards an operating frequency of the system as a coupling coefficient between the transmit and receive resonators becomes smaller. In another embodiment, a receive controller can be configured to control a current delivered to a DC load by comparing an actual current at the DC load to a current requested by the DC load and adjusting an angle or a magnitude of a voltage at the DC load to match the requested current. In another embodiment, a rectifier circuit can act as a controlled voltage source and be configured to tune resonant frequencies between the transmit resonator and the receive resonator. Methods of use are also provided.
US09287037B2
A transformer-bobbin including a winding-frame portion constituted by a middle barrel portion 63, a lower flange portion 62 and an upper flange portion 61, wherein there is provided a slit portion 67 which notches the terminal bed unit 65 and the lower flange portion 62 and concurrently which extends in the centrally approaching and separating direction toward the middle barrel portion 63 side, and wherein at the slit portion 67, there is provided a guide wall surface 68a whose side on the middle barrel portion 63 side is positioned on the lower flange portion side compared with whose side apart from the middle barrel portion 63.
US09287034B2
A printed wiring board has a core base having an opening portion, an inductor component accommodated in the opening portion, and a filler resin filling gap between the component and a side wall of the opening portion. The component has a support layer, a first conductive pattern on the support, an interlayer insulation layer on the support and first pattern, a second conductive pattern on the insulation layer, and a via conductor in the insulation layer and connecting the first and second patterns, the insulation layer includes a magnetic layer and a resin layer covering the magnetic layer, the magnetic layer includes magnetic material and resin material and has a first hole, the insulation layer has a second hole penetrating through the resin layer such that the second hole passes through the first hole and extends to the first pattern, and the via conductor is formed in the second hole.
US09287027B2
An objective of the present invention is to provide a rare earth metal-based permanent magnet with improved adhesion properties. A rare earth metal-based permanent magnet of the present invention as a means for achieving the objective has a laminated plating film, and is characterized in that the plating film comprises as an outermost surface layer a SnCu alloy plating film having a film thickness in a range from 0.1 μm to 2 μm, the composition of the SnCu alloy plating film is 35 mass % or more but less than 55 mass % of Sn and the rest being Cu, and a base plating film having two or more layers including at least a Ni plating film and a Cu plating film which are formed as the lower layer under the SnCu alloy plating film, and among the base plating film, the Ni plating film is located just below the SnCu alloy plating film. A joined structure fabricated using the rare earth metal-based permanent magnet of the present invention exhibits favorable initial adhesion strength when combined with a silicone-based adhesive, and is less deteriorated in adhesion strength even after a moisture resistance test.
US09287026B2
An object is to provide a magnetic material and coil component offering improved magnetic permeability and insulation resistance, while also offering improved high-temperature load, moisture resistance, water absorbency, and other reliability characteristics at the same time. A magnetic material that has multiple metal grains constituted by Fe—Si-M soft magnetic alloy (where M is a metal element that oxidizes more easily than Fe), as well as oxide film constituted by an oxide of the soft magnetic alloy and formed on the surface of the metal grains, wherein the magnetic material has bonding parts where adjacent metal grains are bonded together via the oxide film formed on their surface, as well as bonding parts where metal grains are directly bonded together in areas having no oxide film, and resin material is filled in at least some of the voids generating as a result of accumulation of the metal grains.
US09287021B2
Shelf brackets to conduct electricity to refrigerator shelves are disclosed. An example shelf bracket includes an end configured to engage a support rail, the end having a first area to conduct electricity from the support rail to the shelf bracket, an arm extending from the end to support the shelf, the arm comprising a second area to conduct electricity from the shelf bracket to the shelf, a non-electrically conductive coating applied to substantially all of the shelf bracket except in the first and second areas, a first electrically conductive material applied to at least a portion of the first area, and a second electrically conductive material applied to at least a portion of the second area, wherein the shelf bracket is formed from a third electrically conductive material, the third electrically conductive material to conduct electricity between the first and second areas.
US09287018B2
A method for preparing silver-based electrical contact materials with fiber-like arrangement of reinforcing nanoparticles includes (1) uniformly mixing reinforcement powders and silver matrix powders for ball milling; (2) pouring the obtained composite powders and silver matrix powders into a powder mixing machine for powder mixing; (3) cold isostatic pressing; (4) sintering; (5) hot pressing; and (6) hot extruding to obtain silver-based electrical contact materials with fiber-like arrangement of reinforcing nanoparticles. The method of the present invention can obtain silver-based electrical contact materials with fiber-like arrangement of reinforcing nanoparticles with no specific requirement on processing deformation, and the plasticity and ductility of the reinforcing phase. Furthermore, it has simple processes, low cost and no particular requirements on the equipment. Contact materials prepared by the present method have good resistance to welding and arc erosion, conductivity and a greatly enhanced processing performance.
US09287007B2
A redundancy control circuit includes: a fail address storage unit configured to store a fail address; a shared storage unit configured to store data as to whether a value stored in the fail address storage unit corresponds to both of a first address and a second address; an address comparator configured to compare a value stored in the fail address storage unit with a first input address and a second input address, respectively; and a redundancy controller configured to control a redundancy operation in response to a value stored in the shared storage unit and comparison results of the address comparator.
US09287002B2
A sampling circuit may include a sampling capacitance, an electronic sampling switch, and a switch controller. The electronic sampling switch may have a control input that controls whether the electronic sampling switch is in a sample state or a hold state. The electronic sampling switch may connect the sampling capacitance to an input signal while in the sample state and disconnect the sampling capacitance from the input signal while in the hold state. The switch controller may control the control input to the electronic sampling switch so as to cause the electronic sampling switch to be in the sample state during one period and the hold state during another period. While in the sample state, the switch controller may cause the impedance of the electronic sampling switch that is seen by the input signal to be substantially independent of the voltage of the input signal. The switch controller may include a pre-charge circuit that pre-charges the control input to the electronic sampling switch prior to each commencement of the sample state to approximately the average of the voltage of the input signal and the voltage on the sampling capacitance immediately prior to each commencement of the sample state. The amount of the pre-charging may be substantially independent of the voltage of the input signal.
US09287000B1
A technique is provided for programming a transistor having a source, a drain, a gate, and a channel region between the source and the drain. The gate is above dielectric above the channel region. A gate voltage is about equal to or greater than a breakdown voltage of the gate dielectric in order to break down the gate dielectric into a breakdown state. Current flows between the source and the drain as a result of breaking down the gate dielectric. In response to the transistor being programmed, the current flowing between the source and the drain is not based on the gate voltage at the gate.
US09286999B1
A semiconductor device includes a first input/output (I/O) part buffering command/address (C/A) signals inputted through a first pad part to generate delay address signals, an internal address generator generating a plurality of internal address signals according to a level combination of the delay address signals, and a second I/O part including a plurality of fuses selected by the plurality of internal address signals in a test mode. The plurality of fuses of the second I/O part are programmed according to logic levels of data inputted to the second I/O part through a second pad part to control I/O characteristics of the second I/O part.
US09286987B1
Techniques are provided for preventing program disturb of unselected memory cells during programming of a selected memory cell in a NAND string which includes a continuous charge-trapping layer, either in a two-dimensional or three-dimensional configuration. In such a NAND string, regions between the memory cells can be inadvertently programmed as parasitic cells due to the program voltage and pass voltages on the word lines. For programmed cells, an upshift in threshold voltage due to a parasitic cell can be avoided by providing a higher pass voltage on an adjacent later-programmed word line than on an adjacent previously-programmed word line. For erased cells, an upshift in threshold voltage due to the parasitic cells can be reduced by progressively lowering the pass voltage on the adjacent later-programmed word line. The lowering can occur when memory cells of a lowest target data state complete programming.
US09286985B2
According to one embodiment, a semiconductor device includes a nonvolatile memory, a volatile memory, and a controller. The controller is configured to transition a part of the volatile memory to a self-refresh mode when a request for stopping supplying of power to the nonvolatile memory is received.
US09286983B2
A memory string includes a pass transistor, first memory cells connected in series to a drain terminal of the pass transistor, and first to kth memory cell groups connected in parallel to a source terminal of the pass transistor and each including a plurality of second memory cells connected in series. Here, ‘k’ denotes an integer that is equal to or greater than ‘2’.
US09286982B2
The present invention relates to a flash memory device with EEPROM functionality. The flash memory device is byte-erasable and bit-programmable.
US09286976B2
Described are apparatuses and methods for improving resistive memory energy efficiency and reliability. An apparatus may include a resistive memory cell coupled to a conductive line. The apparatus may further include a driver coupled to the conductive line to drive current for the resistive memory cell during a write operation. The resistance of the driver may be selectively increased for two or more time periods during the write operation for detecting a voltage change on the conductive line. The current for the write operation may be turned off when the voltage change is detected to improve resistive memory energy efficiency and reliability.
US09286975B2
The present disclosure relates to mitigating read disturb in a cross-point memory. An apparatus may include a memory controller configured to select a target memory cell for a memory access operation. The memory controller includes a sense module configured to determine whether a snap back event occurs during a sensing interval; and a write back module configured to write back a logic one to the memory cell if a snap back event is detected.
US09286970B2
A memory includes a word line, a bit line and a complementary bit line. A memory cell has a data node coupled to the bit line and a complementary data node coupled to the complementary bit line. The word line controls access to the memory cell. A circuit is coupled to the bit line and the complementary bit line. The circuit is configured to pull up to a high voltage, pull down to a low voltage, or float the bit line and the complementary bit line based on a first timing of pre-charging and a second timing of write driving. The first timing and the second timing are synchronized.
US09286961B1
A method and apparatus for reducing a number of delay elements used in providing a delayed data strobe signal is disclosed. The method includes determining a number of delay elements of a master delay locked loop (DLL) needed to provide a calibrated delay of a clock signal (i.e. the data strobe). The method also include determining an integer number of half clock periods within the calibrated delay, and determining a second number of delay elements within the calibrated delay. If the integer number of half clock periods within the calibrated delay is zero, a slave DLL may be programmed with the first number of delay elements. However, if the number of half clock periods is non-zero, then a third number of delay elements is calculated by subtracting the second number of delay elements from the first number. Thereafter, the slave DLL is programmed with the third number of delay elements.
US09286960B2
According to one embodiment, each memory chip included in a memory package includes a first storage unit that stores therein first information that is n-bit information and is a comparison target of a chip address, and is used for identifying its own memory chip, a second storage unit that stores therein second information for determining an effective bit of the n-bit first information, and a control unit that determines an effective bit of the n-bit first information and an effective bit of the chip address based on the second information.
US09286944B2
A method of providing a combination of video data (37) and metadata (34) includes obtaining a sequence (23) of images captured by a video camera (5). At least one signal (24) is extracted from the sequence (23) of images, wherein each extracted signal (24) characterizes local temporal variations in at least one of light intensity and color. At least one video compression technique is applied on image data of images from the sequence (23) to obtain compressed video data (37). The extracted signals (24) are extracted from images in a state prior to the application of the at least one compression technique to image data from those images. The compressed video data (37) is provided with metadata (34) for characterizing at least one process in a subject represented in at least part of the images, which process causes local temporal variations in at least one of color and intensity of light captured from the subject. The metadata (34) is at least based on at least one of the extracted signals (24).
US09286940B1
An apparatus having a server is disclosed. The server may be configured to (i) receive via a network a first clip of video generated by a camera, (ii) receive via the network first information to edit the first clip, (iii) receive via the network one or more segments of a second clip of video generated by the camera as identified by the first information and (iv) create a third clip of video by editing the segments according to the first information. The second clip is generally a higher resolution version of the first clip. The third clip may have the higher resolution.
US09286938B1
Systems and methods for generating and presenting different length versions of a video are presented. In one or more aspects, a system is provided that includes an analysis component configured to analyze a video and generate summaries of content included in respective segments of the video, and a summary component configured to generate shortened versions of the video having durations less than the duration of the video based in part on the summaries of the content included in the respective segments of the video, wherein the video is made available for streaming in association with an option to select the video or one of the shortened versions.
US09286934B2
A method and apparatus for data de-duplication is disclosed. Use de-duplication engine (DDE) divides data into regions. The DDE processes the regions in a serial fashion. The DDE clears its hash table before processing the first region. Each region is divided into a number of chunks. A hash is generated for each chunk in a region. When a hash for a chunk is not in a hash table, the hash is stored in the hash table and the chunk is stored on media. When the hash is a duplicate of a hash already in the table, the hash and chunk are discarded and a reference to the previously stored chunk is stored to the media. The DDE does not retain all the hashes from all the regions in the hash table at the same time. The DDE only retains the hashes for the current region being processed and N previous regions where N is a positive integer greater than zero.
US09286932B2
A hard disk drive includes a storage surface, a motor, a read/write had, and a number of regions into which the storage surface is divisible. Data is writable to and data is readable from the storage surface. The motor is to rotate the storage surface at a variable speed. The read/write head is to write data to and read data from the storage surface while the storage surface is rotated by the motor. Each region corresponds to a different speed at which the storage surface is rotated for the read/write head to write data to and read data from the region.
US09286928B1
According to one embodiment, a measurement method is applied to a disk device including a disk, and a head configured to protrude toward the disk when power is supplied thereto. In the method, a reference value for each of areas of the disk is acquired from a measurement-value distribution including pre-measured values that correspond to power supplied to a heater when the head is brought into contact with the disk. In each area, a data group calculated from the distribution and the reference value is acquired. An area where the data group has lower values than in the other areas is selected as a first area to be firstly measured. An area to be measured subsequent to the first area based on the data group is selected.
US09286924B1
A flexible printed circuit assembly includes a flexible printed circuit board including a base portion and a relay portion extending from a first edge of the base portion and capable of being bent relative to the base portion, a first reinforcing member disposed at the relay portion, and a second reinforcing member attached to a first region of the base portion that includes a second edge opposite to the first edge and having an engaging portion. The first region of the base portion is capable of being folded back towards a second region of the base portion that includes the first edge, and the engaging portion of the second reinforcing member is capable of being engaged with the first reinforcing member.
US09286919B1
A magnetic transducer has air-bearing surface (ABS) and includes a main pole, at least one coil, a side shield and a side gap. The coil(s) energize the main pole. A portion of the main pole resides at the ABS. The side gap is between the main pole and the side shield. The side gap is nonmagnetic and includes a first side gap and a second side gap. The first side gap is conformal with the main pole. The second side gap is conformal with the main pole. The first side gap is between the second side gap and the ABS. The second side gap is wider than the first side gap.
US09286910B1
A system for resolving a user's question regarding media at the user's location where the question includes ambiguity as to the context of the question. Context information is acquired from a device or devices at the user's location, and if multiple possible contexts are identified, the system may attempt to resolve the question for more than one of the possible contexts. The system for answering questions and the source of the media may be different and independent.
US09286904B2
A computing device may be configured to output a digital audio stream to an audio playback system for rendering as sound over speakers. The sound may be sampled. Based at least in part on a quality of the sampled sound, the data rate of the digital audio stream may be reduced by reducing a sampling rate and/or by reducing a number of bits per sample. A reduced sampling rate may be determined based on a computed maximum sampling rate of the audio playback system, and/or a reduced number of bits per sample may be determined based on a computed maximum number of bits per sample of the audio playback system. The maximum usable sampling rate and maximum usable number of bits per sample may be determined based on an upper usable frequency within a frequency spectrum of the sampled sound.
US09286902B2
A machine may be configured to generate one or more audio fingerprints of one or more segments of audio data. The machine may access audio data to be fingerprinted and divide the audio data into segments. For any given segment, the machine may generate a spectral representation from the segment; generate a vector from the spectral representation; generate an ordered set of permutations of the vector; generate an ordered set of numbers from the permutations of the vector; and generate a fingerprint of the segment of the audio data, which may be considered a sub-fingerprint of the audio data. In addition, the machine or a separate device may be configured to determine a likelihood that candidate audio data matches reference audio data.
US09286894B1
Recognition techniques may include the following. On a first processing entity, a first recognition process is performed on a first element, where the first recognition process includes: in a first state machine having M (M>1) states, determining a first best path cost in at least a subset of the M states for at least part of the first element. On a second processing entity, a second recognition process is performed on a second element, where the second recognition process includes: in a second state machine having N (N>1) states, determining a second best path cost in at least a subset of the N states for at least part of the second element. At least one of the following is done: (i) passing the first best path cost to the second state machine, or (ii) passing the second best path cost to the first state machine. The foregoing techniques may include one or more of the following features, either alone or in combination.
US09286892B2
Some implementations include a computer-implemented method. The method can include providing a training set of text samples to a semantic parser that associates text samples with actions. The method can include obtaining, for each of one or more of the text samples of the training set, data that indicates one or more domains that the semantic parser has associated with the text sample. For each of one or more domains, a subset of the text samples of the training set can be generated that the semantic parser has associated with the domain. Using the subset of text samples associated with the domain, a language model can be generated for one or more of the domain. Speech recognition can be performed on an utterance using the one or more language models that are generated for the one or more of the domains.
US09286880B2
A masking sound outputting device includes: an inputting unit which receives a picked-up sound signal relating to a picked-up sound; an extracting unit which extracts an acoustic feature amount of the picked-up sound signal; an instruction receiving unit which receives instructions for starting an output of a masking sound; and an outputting unit which, in the case where the instruction receiving unit receives the instructions for starting an output, outputs a masking sound corresponding to the acoustic feature amount extracted by the extracting unit.
US09286875B1
An electronic percussion instrument includes a chair having a seat, a first arm disposed on one side of the seat, and a second arm disposed on an opposite side of the seat. A set of piezoelectric triggers is arrayed along each of the first and second arms and the triggers are positioned to be struck by the thumbs of a percussionist while sitting on the seat of the chair. The triggers are connected to an electronic drum machine. Sequential striking of the triggers with the thumbs of a percussionist sitting in the chair causes corresponding percussion sounds to be played by the electronic drum machine. Additional triggers are disposed on the floor and can be struck with the feet of the percussionist to produce additional percussion sounds. Thus, drum rhythms can be played easily and naturally while sitting in the chair.
US09286866B2
A drum having a vibratory member(s) tensioned over a plurality of tuned staves which acts as a sounding board and having staves which may be joined together with one or more flexible lines. The invention also includes a method of making such a drum and includes variations in the bearing edges of the tuned staves for such a drum.
US09286856B2
A display device is disclosed. The display device has pixels which include three color sub-pixels, for example, red, green, and blue sub-pixels. The pixels also include a white sub-pixel. The display calculates data for the red, green, blue, and white sub-pixels based on data for red, green, and blue sub-pixels.
US09286845B2
An adjacent gradation correcting unit 11 performs processing for correcting gradations of sub-pixels to a video signal X2 after overshoot processing. When determining that a gradation of a target sub-pixel corresponds to a higher liquid crystal application voltage than that of a gradation of an adjacent sub-pixel, and that a gradation difference between the target sub-pixel and the adjacent sub-pixel is large, the adjacent gradation correcting unit 11 corrects the gradation of the adjacent sub-pixel so as to make the gradation difference smaller. In driving a liquid crystal panel 1, a video signal X3 after correction obtained by the adjacent gradation correcting unit 11 is used. With this, when displaying a specific color, such as red, green, or blue, it is possible to suppress a lateral electric field occurring between two sub-pixels that are adjacent to each other, and to improve response speed of the liquid crystal panel 1.
US09286835B2
The present invention provides a driving circuit and a driving method for light-emitting diodes (LEDs), and a display apparatus using the same. The driving circuit comprises a power switch and a dimmer circuit. The method comprising: providing a pulse width modulation (PWM) dimming signal and a high frequency dimming signal; and multiplying the PWM dimming signal and the high frequency dimming signal for providing a driving signal to the power switch. The present invention can improve a dimming effect of the LEDs.
US09286830B2
A pixel circuit has a first capacitor having a first terminal connected with a gate of a driving transistor; a second capacitor connected between a second terminal of the first capacitor and a source of the driving transistor; a first switch applying a reference voltage to a node at which the first capacitor and the second capacitor are connected; a second switch supplying an image signal voltage to the gate of the driving transistor; a third switch supplying an initialization voltage to a drain of the driving transistor and a fourth switch supplying current to the drain of the transistor for emitting light from the current light emitting device.
US09286825B2
The apparatus for driving LED display includes a system control unit having a synchronization signal generator configured to generate a synchronization start signal and a plurality of phase locked loop circuits. Each of the phase locked loop circuits includes a divider coupled to the voltage controlled oscillator and configured to change the sequence of dividing ratios over a modulation period, a sigma delta modulator configured to generate a sequence of random numbers to the divider, and a spread spectrum modulation depth controller coupled to the sigma delta modulator and configured to receive the synchronization start signal from the synchronization signal generator. Upon receipt of the synchronization start signal, the spread spectrum modulation depth controller starts a spread spectrum modulation.
US09286811B2
Selectively concealable indicator assemblies configured to mount behind a wall plate, which provides an interface to interior wiring and is operatively mounted to a wall with a mounting fits tenet. The indicator assembly includes an elongate member and an indicator. The elongate member is disposed between the wall and the wall plate and configured to move between a first position substantially concealed by the wall plate and a second position where at least a portion of the elongate member extends beyond the wall plate. The indicator is disposed on the portion of the elongate member that extends beyond the wall plate when the elongate indicator is in the second position.
US09286806B2
A device for revising a low-altitude flight phase of a flight path of an aircraft includes an input unit configured to allow an operator to input parameters to define an intermediate flight section (Si) which has to be inserted into a low-altitude flight phase, and a processing unit configured to calculate a profile relating to the intermediate flight section (Si) using input parameters, and to automatically insert this profile into the flight phase between a first upstream part (P1) and a second downstream part (P2) so as to establish a revised flight phase (PR).
US09286804B2
Indicator light devices are useful in many applications for indicating properties of physical spaces respectively associated therewith and in physical proximity thereto. The indicator light devices are network-enabled and self-powered, and capable of participating in coordinated power-managed operation to provide a sufficient service life and lower installation and replacement costs. The indicator light devices may be used with or without associated sensors. The various embodiments described herein use various power management techniques singly or in combination to greatly increase the service life of self-power indicator light devices without diminishing their effectiveness in the application. These techniques include operating only the indicator light devices associated with the physical spaces having properties of interest, operating the indicator light devices with synchronized flashing, operating the indicator light devices in accordance with the detection of specific conditions, relevant time operation, in-vicinity activation, and ambient light responsiveness.
US09286797B1
A location for a traffic incident can be determined by a computer system, using data from a first and second sensor along a travel path. A receiving and sending symptom of the traffic incident are detected from a first and second sensor, using traffic flow data from the sensors. The locations of the first and second sensors are determined. The location and traffic flow data from each sensor are used to create a sending and receiving profiles. From the profiles, a convergence formula is build. Using the convergence formula and by determining a convergence point for the sending and receiving symptoms, a time and location of the traffic incident is identified.
US09286795B2
A system for sharing and processing road condition information includes a number of road condition information computer systems within individual vehicles or devices and a virtual road condition information server on a mobile network. The road condition information computer systems are each connected through a peer-to-peer radio, cellular, Wi-Fi, or other similar communications network, and which each operate with a database for displaying road maps, with a database storing average speed data for directions of travel along roadways, and with a location sensor used to determine the location and average speed of the vehicle or device, which are transmitted to other vehicles. The virtual server returns average speed data for road segments, which is displayed on the road maps. The system includes sharing average speed data calculated as well average speed data received from the plurality of vehicles to other vehicles, thereby enhancing the real-time communication of road condition data.
US09286789B2
In one aspect of the disclosed implementations, a device includes one or more motion sensors for sensing motion of the device and providing activity data indicative of the sensed motion. The device also includes one or more processors for monitoring the activity data, and receiving or generating annotation data for annotating the activity data with one or more markers or indicators to define one or more characteristics of an activity session. The device also includes one or more feedback devices for providing feedback, a notice, or an indication to a user based on the monitoring. The device further includes a portable housing that encloses at least portions of the motion sensors, the processors and the feedback devices.
US09286787B2
A low cost, robust, wireless sensor that provides an extended period of operability without maintenance is described. The wireless sensors are configured to communicate with a base unit or repeater. When the sensor unit detects an anomalous ambient condition (e.g., smoke, fire, water, etc.) the sensor communicates with the base unit and provides data regarding the anomalous condition. The sensor unit receives instructions to change operating parameters and/or control external devices.
US09286780B2
A smoke detector includes a drift chamber and an ionization chamber formed by a first electrode and a second electrode. Electric charges are generated by ionization of the air. The drift chamber separated from the ionization chamber by the second electrode. The smoke particles penetrates from the environment to a detector inside the drift chamber. The electrical potential of first electrode exceeds a critical electric potential value for generating a corona discharge in the vicinity of the first electrode. The second electrode has openings for the electric charges generated in the ionization chamber to move to the drift chamber. The electric potential of the second electrode allows the electric charges in the drift chamber to move from the second electrode to the third electrode. The electric field between the second and third electrodes is at least 100 times weaker than the electric field between the first and second electrodes.
US09286775B2
An image signal processing DSP subjects an image captured by an imaging element having a zoom lens to image processing for identifying a tracking target. In accordance with zoom information generated by the image signal processing DSP, the main CPU controls the zoom lens; and controls a turn table that moves the imaging element in panning and tilting directions in accordance with pan and tilt information, to track the tracking target. During tracking of the tracking target, a determination is made, from information about movements of the tracking target generated by the image signal processing DSP, as to whether or not the target to be tracked has intruded the inside of the area from the outside. In a case where the target has intruded the inside of a preset area from the outside, an alarm command is produced when the target continually remains in the area for; e.g., one second.
US09286774B2
A tactile sensation providing apparatus includes a tactile output unit configured to contact a part of a human body; a connection unit including a wire connected to the tactile output unit and made of a flexible and elastic material, and a tube enclosing the wire; and a driving unit to supply a driving force to the connection unit.
US09286772B2
A security control apparatus, system and method are provided. The security control apparatus includes a wireless communication element that supports a plurality of wireless communication protocols. The wireless communication element is configured to provide wireless communications with a user interface device and at least one premise-based device. A remote communication element is configured to provide remote communications with a monitoring center. A processor is in communication with the local wireless communication element and the remote communication element. The processor is configured to use the wireless communication element to communicate with the user interface device to receive local control and configuration data. The processor is also configured to use the remote communication element to communicate data associated with at least one of a life safety feature and life style feature with the monitoring center.
US09286765B2
Various embodiments of the present disclosure are directed to a gaming system and method providing a game providing an award if a shape of a symbol displayed at a symbol display area corresponds to a shape of that symbol display area. Other embodiments of the present disclosure are directed to a gaming system and method providing a game having a player-adjustable volatility. In certain embodiments, the game is the above-described game, while in other embodiments, the game is a different game. Generally, in certain such embodiments, the gaming system enables a player to tailor the overall volatility of a play of the game to the player's preference by selecting a desired combination of symbol display areas to employ for a play of the game.
US09286759B2
A wagering game system and its operations are described. In some embodiments, the operations include detecting an indication of a benefit available to a first player account via a wagering game venue; and selecting a second player account linked to the first player account as a social contact. The operations can further include configuring a persistent object to provide access to the benefit available to the first player account; and transferring the persistent object from the first player account to the second player account.
US09286753B2
The present invention involves methods and devices for controlling many aspects of a player's gaming experience, including game themes presented, game denomination, pay models, content and promotions. Some implementations of the invention provide a casino operator the necessary tools to create subsets Of customers, often referred to herein as “communities,” and to control the gaming experiences of players in these communities. In some such implementations, communities May be created and/or modified according to various criteria, some of which may be weighted more heavily than others. Specific marketing messages, promotions, etc., may be provided to attract and retain players having similar characteristics and preferences.
US09286752B2
Systems and methods receive digital images from online sources. The digital images are analyzed and various objects are recognized within the digital images. The recognized objects may be faces of persons appearing in the digital images. A subset of the digital images is selected according to selection rules applied to the recognized objects. The selected recognized objects are incorporated into a wagering game. For example, the recognized objects may be incorporated onto symbols of wagering game.
US09286746B2
A gaming device including a plurality of symbol generators adapted to generate a plurality of symbols at a plurality of symbol positions. In one embodiment, a player selects a first symbol position, the selected symbol position is activated and the gaming device reveals whether a terminator is associated with the selected symbol position. In this embodiment, the player continues selecting symbol positions (and the gaming device continues activating the selected symbol positions) until a terminator is revealed to be associated with a selected symbol position. After a terminator is revealed, the gaming device randomly generating a symbol at each of the activated symbol positions. The gaming device determines an outcome based on the symbols or combinations of symbols generated at the activated symbol positions and provides the player the determined outcome.
US09286745B2
A game control method according to the present invention comprises: a downloading step conducted by a server of downloading exchange-ratio changing data for use in determining the currency value of a credit in a gaming terminal to the gaming terminal; an exchange ratio determining step conducted by the gaming terminal of determining the exchange ratio between credits and currency values using the exchange-ratio changing data downloaded from the server, and an exchanging step conducted by the gaming terminal of exchanging a monetary value for a credit and/or exchanging a credit for a monetary value, based on the determined exchange ratio.
US09286741B2
A method and apparatus for controlling access from a first area to a second area includes receiving an identity signal from an identifier input device, and checking for stored data indicating that the identity represented by the identity signal is registered as present in the first area. If a predetermined access requirement is fulfilled, then a pass signal at the first access controller is generated. To control access from the second area to a third area, an enter message is sent to a second controller with at least the identity and data indicating that the identity is present in an access area of the second controller. An exit message is sent to a third controller controlling access to the first area, including at least the identity and data indicating that the identity is not present in an access area of the third controller.
US09286740B2
The invention relates to a method for displaying information, using a mobile identification provider (10) and an independent display unit (20), wherein said mobile identification provider (10) serves for an activation of a security system, said mobile identification provider (10) has an electronic unit (11), and said electronic unit (11) is used for data communication (30) with a vehicle-side part, vehicle-side information is transmitted from the vehicle-side part to the electronic unit (11) via the data communication (30), said vehicle-side information is stored in a data memory (12), said electronic unit (11) communicates with the independent display unit (20) via a communication connection (40), and said vehicle-side information is transmitted to said independent display unit (20) via said communication connection (40) and displayed thereon.
US09286734B2
The system measures time of at least one object on the basis of passing a finish line and includes a camera with a photosensitive sensor and a lens for registering an image of the line. The image is sent to a processor for processing. Timing means deliver a timing signal to the processor. The system is at least partially automatically aligned. It thereto comprises a first active optical indicator that is located at a predefined location with reference to the line of passage, which indicator is detected as part of the image registered by the camera so as to obtain detection data. The system further includes a camera adjustment arrangement for adjustment of the orientation of a center axis of the camera, said adjustment being specified by the processor on the basis of the detection data.
US09286731B2
Described herein are processes and devices that coalesced and/or collapse areas in a region of a virtual universe to conserve computing resources. Some embodiments are directed to detecting an indication to reduce usage of a computing resource in the virtual universe and, in response, determining the first area of the virtual universe for coalescing and collapsing into the second area of the virtual universe. In some embodiments, the first area comprises a plurality of virtual universe objects. Some embodiments are further directed to selecting a first set of the plurality of virtual universe objects for moving from the first area into the second area, coalescing the first set of the plurality of virtual universe objects into the second area from the first area, and, in response, collapsing the first area of the virtual universe.
US09286724B2
A book for use in an augmented reality system comprises a plurality of leaves, each side forming a page of the book, with each page comprising a fiduciary marker. The book also includes a cover having larger dimensions than the book's leaves. Thus, the cover's extremhities extend beyond the outer edges of the pages. The inside of the cover comprises a first high contrast pattern along at least a first such extremity. An entertainment device for use in the augmented reality system comprises input means to receive a video image of the book, and image processing means to estimate a position and orientation of the book from a fiduciary marker of the book captured in the video image, to estimate a position and orientation of the first high contrast pattern, and to distinguish between one or more leaves of the book being turned independently of the cover of the book.
US09286719B2
A method including displaying a three-dimensional (3D) image of a lung, receiving a selection of an airway of the lung and displaying a two-dimensional (2D) cross-section image of the airway perpendicular to the airway's long axis, wherein the display of the 2D cross-section image occurs almost immediately after the selection of the airway is received.
US09286716B2
A static model is populated with graphics objects by identifying a first graphics object that is associated with the static model, creating a first plurality of graphics objects where each graphics object in the first plurality of graphics objects comprises an instance of the first graphics object, placing each graphics object in the first plurality of graphics objects into a respective first position, and simulating a motion path for each graphics object in the first plurality of graphics objects from their respective first position to a respective second position.
US09286712B2
A map element parameterized in a two-dimensional (2D) coordinate system is applied to to three-dimensional (3D) geometry, parameterized in a 3D coordinate system, of a geographic area with which the map element is associated. The 3D geometry is rendered according to the selected perspective of a virtual camera. An approximate distance between the virtual camera and the 3D geometry is compared to a threshold value. A position of the map element is determined relative to the 3D geometry using (i) a linear transformation between the 2D coordinate system and the 3D coordinate when the approximate distance is smaller than the threshold value, and (ii) a non-linear transformation between the 2D coordinate system and the 3D coordinate system when the approximate distance is larger than the threshold value.
US09286711B2
Technology is described for representing a physical location at a previous time period with three dimensional (3D) virtual data displayed by a near-eye, augmented reality display of a personal audiovisual (A/V) apparatus. The personal A/V apparatus is identified as being within the physical location, and one or more objects in a display field of view of the near-eye, augmented reality display are automatically identified based on a three dimensional mapping of objects in the physical location. User input, which may be natural user interface (NUI) input, indicates a previous time period, and one or more 3D virtual objects associated with the previous time period are displayed from a user perspective associated with the display field of view. An object may be erased from the display field of view, and a camera effect may be applied when changing between display fields of view.
US09286710B2
Implementations generally relate to generating photo animations. In some implementations, a method includes receives a plurality of photos from a user. The method also includes selecting photos from the plurality of photos that meet one or more predetermined similarity criteria. The method also includes generating an animation using the selected photos.
US09286704B2
A technique is provided for a graphical user interface on a computer. The technique includes receiving messages individually corresponding to resources being monitored, displaying rows in a table, and generating bar graphs of the messages respectively corresponding to the resources in the rows. Each of the bar graphs displays a color coded scheme to visually distinguish severity of the messages in each of the rows for the resources. The bar graphs display the severity of the messages for one resource per the given row without requiring user intervention to view severities of the messages displayed by the color coded scheme, without requiring user intervention to view a total number of messages for the given row, while maintaining a same row height regardless of the total number of messages for the given row, and without changing a table size including a table height and a table width of the table.
US09286702B2
A radiographic imaging system is adapted to reconstruct a tomographic image in a given cross section of a subject from projection images of a subject acquired in tomosynthesis imaging. The radiographic imaging system comprises a frequency filtering processor for producing band limiting image signals having different frequency response characteristics from projection image signals corresponding to the projection images; a non-linear conversion processor for performing non-linear conversion of band limiting image signals to reduce a portion of band limiting image signals exceeding a given value; an integration processor for adding up band limiting image signals having undergone non-linear conversion through the non-linear conversion processor to produce converted image signals; and a back projection processor for reconstructing the tomographic image in the given cross section of the subject from the converted image signals corresponding to the projection images.
US09286695B2
Systems and methods for tracking points within an encasement are provided. According to an aspect of the invention, a processor designates an encasement at a first location within a first image acquired at a first time; identifies points to track within the encasement; determines characteristics of the points to track; tracks the points over time based on the characteristics; and determines a second location of the encasement within a second image acquired at a second time based on positions of the tracked points at the second time. Identifying the points to track may include identifying points within the encasement that are significant and persistent.
US09286684B2
Aspects of the present invention relate to systems, methods, and computer program products for measuring and compensating for optical distortion. The system includes a plurality of reference marks; a recording device configured to record a first orientation and a first position of a plurality of reference marks relative to a pointing angle of the recording device when an object is located outside of a field of view of a recording device, the recording device configured to record a second orientation and a second position of a plurality of reference marks relative to the pointing angle of the recording device when an object is located inside the field of view; and a processor configured to compare the first orientation and the first position of the plurality of reference marks to the second orientation and the second position of the plurality of the reference marks for measuring distortion of the object.
US09286683B1
Approaches to enable a computing device, such as a phone or tablet computer, to detect when text contained in an image captured by the camera is sufficiently close to the edge of the screen and to infer whether the text is likely to be cut off by the edge of the screen such that the text contained in the image is incomplete. If the incomplete text corresponds to actionable text associated with a function that can be invoked on the computing device, the computing device may wait until the remaining portion of the actionable text is captured by the camera and made available for processing before invoking the corresponding function on the computing device.
US09286682B1
Alignment techniques are described that automatically align multiple scans of an object obtained from different perspectives. Instead of relying solely on errors in local feature matching between a pair of scans to identify a best possible alignment, additional alignment possibilities may be considered. Grouped keypoint features of the pair of scans may be compared to keypoint features of an additional scan to determine an error between the respective keypoint features. Various alignment techniques may utilize the error to determine an optimal alignment for the scans.
US09286677B2
In a method for estimating an orientation of a cardiac long axis from corresponding early frame and late frame images implemented in a computerized processor, a bounding box of the myocardium is defined in the late frame image and the bounding box is applied to the early frame image. A main axis of the image of the early frame within the bounding box is estimated, and the image of the early frame is oriented according to the estimated main axis. A main axis of the image of the late frame within the bounding box is also estimated, and the late frame image is reoriented according to the estimated main axis. The estimated main axis of the early frame to the estimated main axis of the late frame are compared, and in attribute of the comparison result is made available as an output from the processor.
US09286673B2
The invention relates generally systems for correcting distortion in a medical image and methods of use thereof. Methods and systems for displaying a medical image of a lumen of a biological structure, generally comprise obtaining image data of a lumen of a biological structure from an imaging device, correcting the image data for translational distortions, in which correcting is accomplished without reference to another data set, and displaying a corrected image.
US09286669B2
A model is defined by a plurality of first positions on an edge extracted from a model image and a changing direction of the edge in each of the first positions. An image processing apparatus calculates a changing direction of an edge in a second position of an input image corresponding to the first position on the edge of the model image. The image processing apparatus accepts an instruction associated with a permissible value of the changing direction of the edge. The image processing apparatus calculates a similarity degree of the first position and the second position corresponding to the first position based on the accepted instruction, the changing direction of the edge in the first and second position. The image processing apparatus determines whether a specific area in the input image is similar to the model or not based on the calculated similarity degree in the second positions.
US09286659B2
A system, method, and computer program product are provided for multi-sample processing. The multi-sample pixel data is received and is analyzed to identify subsets of samples of a multi-sample pixel that have equal data, such that data for one sample in a subset represents multi-sample pixel data for all samples in the subset. An encoding state is generated that indicates which samples of the multi-sample pixel are included in each one of the subsets.
US09286657B1
Systems and methods for processing an image through an ordered series of image filters (i.e., an image filter chain) to produce an output image. The systems and methods of the present disclosure function to partition or break-up an image into dynamically sized tiles which are processed efficiently (e.g., using minimal memory), quickly and on-demand. The systems and methods allow tile sizes to be calculated dynamically based on what each image filter in an image filter chain needs. By processing each tile on-demand, significant memory and time savings are achieved because only the parts of an image required for display are processed. Further, such functionality allows for decoding of only a portion of the image, which requires less memory and operates much faster than if the entire image was decoded.
US09286654B2
An image scaling processor includes: a coefficient computing circuit that calculates interpolation coefficients to be used in an image scaling process; a multiplier that multiplies input image data by the interpolation coefficients provided from the coefficient computing circuit such that the interpolation coefficients respectively correspond to input pixels constituting the input image data; an adder that iteratively adds pieces of multiplied data output from the multiplier and obtains a total sum of the pieces of multiplied data for a predetermined number of the input pixels; a selector that outputs a total sum of the multiplied data at a timing at which the total sum of the pieces of multiplied data is obtained for the predetermined number of the input pixels; and a shift circuit that shifts an output of the selector to adjust a bit count of the output image data to a bit count of the input image data.
US09286652B2
According to an embodiment, provided is a screen generating apparatus that includes: a position information acquirer that acquires a screen position information file that sets a font size of a font included in a screen and position information of an image or a part included in the screen; a screen display size acquirer that acquires a screen display size of a display devise as a target display; a magnification calculator that calculates a magnification by using a predetermined screen display size and the acquired screen display size; a font size determiner that determines a font size in the display devise as the target display based on the calculated magnification; a converter that converts the screen position information file based on the calculated magnification and the determined font size; and a screen generator that generates a screen compatible with the converted screen position information file.
US09286647B2
A computer-implemented method for drawing graphical objects within a graphics processing pipeline is disclosed. The method includes determining that a bypass mode for a first primitive is a no-bypass mode. The method further includes rasterizing the first primitive to generate a first set of rasterization results. The method further includes generating a first set of colors for the first set of rasterization results via a pixel shader unit. The method further includes rasterizing a second primitive to generate a second set of rasterization results. The method further includes generating a second set of colors for the second set of rasterization results without the pixel shader unit performing any processing operations on the second set of rasterization results. The method further includes transmitting the first set of pixel colors and the second set of pixel colors to a raster operations (ROP) unit for further processing.
US09286643B2
The present invention may provide a method and apparatus for building a personalized memory compilation for members of a group: providing digitally encoded images, text and other data; analyzing data; eliciting a characteristic of data; selecting a plurality of the provided data; arranging the provided data, to generate a personalized memory compilation; wherein at least one of a selecting or an arranging step is performed in response to elicited characteristics. The invention may comprise a collaborative method and apparatus for gathering, enriching, preserving, and sharing memories for members of a group using the combination of 1) collaboration through nominal group recall and 2) recording of personal preferences to produce a digital asset that contains a unique blend of selected profiles, images, stories, personalized notes, and other relevant content from more than one group member to constitute a more complete and accurate rendering of an important occasion experienced by the group.
US09286637B1
The invention is directed to a method and system for providing an interface including modular customizable elements for implementation by a system user. The method and system have particular application for financial accounts, such as credit card accounts. The interface may adapt in response to user behaviors. However, the user may also customize features of the interface. Thus, a behavioral monitoring and analysis system is provided for monitoring account holder spending behaviors and analyzing the spending behaviors. Account holder customization tools may be presented to the account holders through a user interface, the account holder customization tools allowing account holders to modify a user interface display of account related parameters by inputting parameters into a computing system. An experience customization engine may be implemented by a processor for receiving input from both the behavioral monitoring and analysis system and the account holder customization tools.
US09286630B2
An information processing system, an information processing apparatus, an information processing method, and an information record medium that are controlled to generate an operation effect sound that differs for each user of a card upon an operation for electronic money are provided. A card 10 records user information 12, balance information 13, and audio data 14. The card 10 makes a settlement of electronic money with a vending machine 20 to buy a commodity. When the card 10 is presented to the vending machine 20, it reads the user information 12, the balance information 13, and the audio data 14 from the card 10 through wireless communications. The vending machine 20 makes a settlement on the basis of both information of the commodity that a user has selected and the balance information 13. As a result, the vending machine 20 provides the selected commodity to the user. On the other hand, with audio data 14, at a predetermined timing of the settlement, a predetermined sound is output. Audio data may be stored only in the vending machine 20 or both in the card 10 and in the vending machine 20. A sound that differs for each user and for each event is output.
US09286620B2
Network devices add annotation information to network packets as they travel through the network devices. The network devices may be switches, routers, bridges, hubs, or any other network device. The annotation information may be information specific to the network devices, as opposed to simply the kinds of information available at application servers that receive the network packets. As just a few examples, the annotation information may include switch buffer levels, routing delay, routing parameters affecting the packet, switch identifiers, power consumption, and heat, moisture, or other environmental data.
US09286615B2
Embodiments disclosed herein relate to methods, devices, and computer systems thereof for visibly or non-visibly indicating a subject has received a medical treatment. In certain embodiments, a subject receives an information mark in conjunction with a medical treatment. In certain embodiments, the information mark includes unique information relating to the subject. In certain embodiments, devices, computer systems, and methods relate to reading an information mark on a subject, and optionally determining if further medical treatment of the subject is warranted. In certain embodiments, receipt of an information mark entitles a subject to a reward.
US09286614B2
An electronic digital direct-mail collateral. In an embodiment, the device comprises a card stock mailer similar to a CD case, center hinged and printed with branded advertising information and graphic. The device may further comprise video, audio and cell phone operations.
US09286612B2
An integrated system for managing changes in regulatory and nonregulatory requirements for business activities at an industrial or commercial facility. Application of this system to environmental, health and safety activities, and to food, drug, cosmetic, and medical treatment and device activities, are discussed as examples. The system: provides one or more databases that contain information on operations and requirements concerning an activity or area of business; receives information on regulatory and nonregulatory changes that affect operations of the business; converts these changes into changes in data entry forms, data processing and analysis procedures, and presentation (by printing, electronic display and/or distribution) of data processing and analysis results to selected recipients, without requiring the services of one or more programmers to re-key and/or reformat the items affected by the change; and implements receipt of change information and dissemination of data processing and analysis results using the facilities of the Internet.
US09286603B2
The invention provides a method of managing an activity, including: a user making a request to engage in an activity with a first of a plurality of providers; and the user presenting to the first provider with a personal data storage device, the device provided with identification data to identify the user and a user profile comprising a plurality of sets of user profile data, each set of user profile data pertaining to at least one of the plurality of providers; wherein the user's request to engage in the activity is assessed according to one or more sets of the user profile data.
US09286602B2
A method of securely communicating a message for a financial transaction from a first correspondent to one or more recipients. The method comprises dividing the message into at least two portions. Each portion is intended for a recipient. Each portion intended for receipt by one of the recipients is encrypted with that recipient's public key. The message is signed and transmitted to one of the recipients to enable the recipient to verify the message and further transmit the message to a further recipient.
US09286599B2
A method, computer program product, and system for redacting content in online meetings is described. A method may comprise receiving, via one or more computing devices, a selected portion of content to redact in a first online meeting. The method may further comprise determining, via the one or more computing devices, if a participant of the first online meeting is in an un-trusted location. The method may additionally comprise, in response to determining that the participant of the first online meeting is in the un-trusted location, redacting, via the one or more computing devices, the selected portion of content from content available to the participant in the first online meeting.
US09286596B2
A system and method for conducting an electronic signing ceremony is provided. The electronic signing ceremony may include a number of defined steps performed by one or more people on a number of documents in a predetermined order. An activity, such as providing a digital signature, may be associated with each document and/or page of each document. The electronic signing ceremony system and method consolidates and streamlines the process of originating, organizing, signing, verifying, storing, and retrieving multiple documents requiring multiple signatures from one or more people virtually anywhere and at any time.
US09286593B1
A system and method for delivering a product such as a pharmacy bottle from a conveyor system to a delivery container via a delivery chute. A control system in communication with the components of the system detects when a product is ready for release into the chute for delivery based on information obtained by a scanner on the conveyor system.
US09286578B2
The present disclosure involves computer-implemented methods, software, and systems for determining a most suitable address for a master data object instance for a given usage in a business transaction document, master data object, or business process. A computer-implemented method includes determining, using at least one computer, an address determination sequence, applying the address determination sequence to available address instances of a master data object instance, identifying a most suitable address from among the available instances, and retrieving an address value from the identified most suitable address instance.
US09286574B2
A computer-implemented method for layered training of machine-learning architectures includes receiving a plurality of data elements wherein each data element is associated with a timestamp, determining a training window for each model layer of a layered stack of model layers, determining a plurality of training data elements for each training window by identifying the data elements with timestamps corresponding to each of the training windows, identifying a previous checkpoint for each model layer wherein the previous checkpoint for each model layer is generated by a parent model layer, training each model layer with the determined training data elements for each model layer and the identified previous checkpoint for each model layer, generating a plurality of current checkpoints wherein each current checkpoint of the plurality of current checkpoints is associated with a model layer, and storing the plurality of current checkpoints at the memory.
US09286571B2
Technologies are generally provided for maintaining performance level of a database being migrated between different cloud-based service providers employing machine learning. In some examples, data requests submitted to an original data store/database may be submitted to a machine learning-based filter for recording and analysis. Based on the results of the data requests and the filter analyses, new key value structures for a new data store/database may be created. The filter may assign performance scores to the original data requests (made to the original data store) and data requests made to the newly-created key value structures. The filter may then compare the performance scores associated with the created key value structures to each other and to performance scores associated with the original data requests and may select the created key value structures with performance scores that are at least substantially equal to those of the original data requests for the new data store.
US09286567B1
Systems, methods and articles of manufacture for providing support information for a software application and generating a knowledge database of support information. A computer system generates a page of the software application displayable on a display. The page has a support button selectable by a user. In response to selection of the support button, the computer accesses support information regarding the page from a knowledge database that is separate from the software application. The computer generates a support page displayable on the display which includes the support information from the knowledge database. The knowledge database is updated at least partly based on analytical data regarding user access of the support information.
US09286558B1
An interactive postage stamp displayable on a mail item 102 evidencing payment of postage, and represented by an encoded image framed by an interactive frame that includes at least one embedded icon activated by scanning the interactive frame causing the activation of the at least one embedded icon, where upon activation the at least one embedded icon may be engaged for accessing the multimedia content linked to the interactive postage stamp, and for controlling the review of the multimedia content using control commands represented by the activated at least one embedded icon or at least one hyperlink within the activated interactive frame.
US09286552B2
An image forming apparatus includes a communication interface unit which receives print data, an image forming unit which prints the received print data, a volatile memory which, if the received print data is data that needs to be stored, stores the received print data, and a controller which, if a power-off command regarding the image forming apparatus is input, backs up print data stored in the volatile memory in a storage medium connectable to the image forming apparatus and converts an operation mode of the image forming apparatus to a power-off mode.
US09286550B2
An image forming apparatus that operates according to given operational conditions, comprising: a target power consumption receiving unit configured to receive a target value for power consumption; an option receiving unit configured to receive options selected by a user from among a plurality of options defining the operational conditions; a basic data storage unit storing therein basic data for each of the options; a calculation unit configured to calculate the estimated power consumption from the basic data according to the options selected by the user; an excess informing unit configured to inform the user when the estimated power consumption is greater than the target value; and an alternative option informing unit configured to inform the user of an alternative option when the estimated power consumption is greater than the target value, the alternative option reducing the estimated power consumption to be equal to or less than the target value.
US09286546B2
Methods, systems, and apparatus for identifying labels for image collections are presented. In one aspect, a method includes obtaining a collection of images; obtaining, for each image in the collection of images, image similarity data that indicates a measure of similarity of the image to other images in the collection of images; generating, based on the similarity data, two or more image clusters from the collection of images, each image cluster including one or more images from the collection of images; for each image cluster: obtaining, for each image in the image cluster, a set of image labels; generating, from each set of image labels obtained for each image in the image cluster, a set of cluster labels; selecting one or more cluster labels from the set of cluster labels; and identifying the selected cluster labels as a set of collection labels for the collection of images.
US09286545B1
In one aspect, a system and method is provided that matches images that are associated with street addresses with images that are associated with locations that are stored with respect to another reference system, such as latitude/longitude. If the images match, the street address is associated with the location. In a further aspect, text contained in the images is extracted and associated with the street address as well.
US09286541B1
A system that removes underlines in text appearing in captured images in multiple stages. The improved system rejects most text regions that do not require underline removal quickly and performs detailed underline detection and removal on a small number of regions.
US09286540B2
In techniques for fast dense patch search and quantization, partition center patches are determined for partitions of example image patches. Patch groups of an image each include similar image patches and a reference image patch that represents a respective patch group. A partition center patch of the partitions is determined as a nearest neighbor to the reference image patch of a patch group. The partition center patch can be determined based on a single-nearest neighbor (1-NN) distance determination, and the determined partition center patch is allocated as the nearest neighbor to the similar image patches in the patch group. Alternatively, a group of nearby partition center patches are determined as the nearest neighbors to the reference image patch based on a k-nearest neighbor (k-NN) distance determination, and the nearest neighbor to each of the similar image patches in the patch group is determined from the nearby partition center patches.
US09286531B2
An image forming system includes a target-log-image extracting unit and a relevant-log-image extracting unit. The target-log-image extracting unit is configured to extract a log image as a target log image likely to have been generated by use for a specific purpose of an image forming apparatus when text information extracted from the log image of the image forming apparatus by optical character recognition includes a specific phrase. The relevant-log-image extracting unit is configured to extract a log image similar to the target log image as a relevant log image based on a specific feature of the target log image extracted by the target-log-image extracting unit.
US09286520B1
Methods and systems for real-time road flare detection using templates and appropriate color spaces are described. A computing device of a vehicle may be configured to receive an image of an environment of the vehicle. The computing device may be configured to identify a given pixels in the plurality of pixels having one or more of: (i) a red color value greater than a green color value, and (ii) the red color value greater than a blue color value. Further, the computing device may be configured to make a comparison between one or more characteristics of a shape of an object represented by the given pixels in the image and corresponding one or more characteristics of a predetermined shape of a road flare; and determine a likelihood that the object represents the road flare.
US09286510B2
Systems, electronic devices, and methods for redeeming user activity level or other desired user behaviors for virtual currency are disclosed. In some implementations, a method includes: at a computer system, obtaining user activity information indicating an activity level of a user; and computing an in-application credit based on the activity level. The in-application credit can be redeemed by the user in an associated application. The in-application credit can be redeemed by the user for a coupon that can be applied towards out-of-application purchases. In some implementations, the activity level is determined in accordance with (i) a motion parameter reported by an activity sensor of an electronic device associated with the user, (ii) information obtained from a cell phone tower or a GPS device (e.g., using cell tower triangulation techniques); and (iii) self-reported user activity information. In some implementations, the method also includes converting the in-application credit for out-of-application purchases.
US09286505B2
Apparatus, methods, and computer-readable media are provided for segmentation, processing (e.g., preprocessing and/or postprocessing), and/or feature extraction from tissue images such as, for example, images of nuclei and/or cytoplasm. Tissue images processed by various embodiments described herein may be generated by Hematoxylin and Eosin (H&E) staining, immunofluorescence (IF) detection, immunohistochemistry (IHC), similar and/or related staining processes, and/or other processes. Predictive features described herein may be provided for use in, for example, one or more predictive models for treating, diagnosing, and/or predicting the occurrence (e.g., recurrence) of one or more medical conditions such as, for example, cancer or other types of disease.
US09286488B2
Disclosed are a system and method of performing secure computations on a protected database. Embodiments of the method provide, in a secure processor, a database of cryptographically hashed values based on a database of cleartext values, receive a cryptographically hashed query value as input into the secure processor wherein the query value is a hash of a cleartext value that corresponds to a cleartext query, perform a comparison operation within the secure processor to determine the presence of the hashed query value within the database of cryptographically hashed values and provide the results of the comparison operation to an external interface of the secure processor, wherein the contents of the database of cryptographically hashed values and the comparison operations are encapsulated within the secure processor and unexposed externally therefrom.
US09286486B2
Disclosed are systems, methods and computer program products for copying encrypted and unencrypted files between data storage devices. In one aspect, the system detects a request to copy a file from a first data storage device to a second data storage device, determines one or more parameters of the copied file, the first data storage device and the second data storage device, selects, based on the one or more parameters, a file encryption policy for the copies file, and applies the selected encryption policy to the copied file.
US09286484B2
Techniques for utilizing security criteria to implement document retention for electronic documents are disclosed. The security criteria can also limit when, how and where access to the electronic documents is permitted. The security criteria can pertain to keys (or ciphers) used to secure (e.g., encrypt) electronic files (namely, electronic documents), or to unsecure (e.g., decrypt) electronic files already secured. At least a portion of the security criteria can be used to implement document retention, namely, a document retention policy. After a secured electronic document has been retained for the duration of the document retention policy, the associated security criteria becomes no longer available, thus preventing subsequent access to the secured electronic document. In other words, access restrictions on electronic documents can be used to prevent access to electronic documents which are no longer to be retained.
US09286480B2
An information processing device includes a processing-type accepting unit that accepts a type of first processing of data, a data accepting unit that accepts post-processing data, the post-processing data being data on which the first processing accepted by the processing-type accepting unit has been executed, and a data processing unit that determines a data confidentiality level indicating a degree of confidentiality of the post-processing data, on a basis of a first confidentiality level associated with the type of the first processing, and executes second processing according to the data confidentiality level with respect to the post-processing data.
US09286472B2
A packet handling system is disclosed that can include at least one main processor, a plurality of offload processors connected to a memory bus and configured to provide security related services on packets prior to redirection to the main processor; an arbiter connected to each of the plurality of offload processors, the arbiter capable of scheduling resource priority for instructions or data received from the memory bus; and a virtual switch respectively connected to the main processor and the plurality of offload processors using the memory bus, with the virtual switch capable of receiving memory read/write data over the memory bus, and further directing at least some memory read/write data to the arbiter.
US09286470B2
A method for protecting a volatile memory against a virus, wherein: rights of writing, reading, or execution are assigned to certain areas of the memory; and a first list of opcodes for which the access to the areas is authorized or forbidden is associated with each of these areas.
US09286456B2
A system that incorporates teachings of the subject disclosure may include, for example, obtaining a group of facial objects detected from an image captured by a camera coupled with a media device where the facial objects correspond to a plurality of users, determining authentication information for each of the plurality of users based on the facial objects, and providing the authentication information to a group of content service systems for enabling the media device to access aggregated media services from the group of content service systems. Other embodiments are disclosed.
US09286450B2
Embodiments of the invention are directed to a system, method, and a computer program product self-selected user access based on specific authentication types. The system typically including a memory, a processor, and a module configured to receive from a user, a user-selected preference, wherein the user-selected preference comprises one or more authentication types desired by the user; determine a level of authentication from a plurality of levels of authentication are associated with the one or more authentication types associated with the user-selected preference; initiate the presentation of a user interface that enables the user to select one or more application functions, wherein the one or more application functions are associated with the determined level of authentication; receive from a user, a selection of one or more application functions.
US09286447B2
A portable digital vault and related methods are disclosed that can provide a digital equivalent to the physical act of lending copyrighted content (such as a book or CD) while also providing security to prevent copying of the content. The vault acts as a self-contained authority that contains permissions relating to actions that can be taken with respect to the vault and vault contents. Vault contents can be moved between vaults, vaults can be moved between computing devices, and a vault and its contents can be moved together as a single unit. A vault can store any type of content, such as digital books, audio and video. In some embodiments, the vault can be issued by a government authority and contain currency note information that allows the vault to be used as cash. A vault can also serve as a receipt of a digital legal contract.
US09286441B2
A point-of-care computer system is provided, including a display positioned in a point-of-care location. The point-of-care computer includes hardware coupled to a frame of a hospital bed.
US09286434B2
Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes generating a photomask for forming a DSA directing pattern overlying a semiconductor substrate. The DSA directing pattern is configured to guide a self-assembly material deposited thereon that undergoes directed self-assembly (DSA) to form a DSA pattern. Generating the photomask includes identifying placement of DSA target patterns in a design layout. The DSA target patterns are grouped into groups including a first group and a first group boundary is defined around the first group. The method further includes determining if a neighboring DSA target pattern to the first group boundary is at least a predetermined minimal keep-away distance from an adjacent DSA target pattern that is within the first group boundary. The method also includes determining if the DSA target patterns in the first group are DSA compatible. An output mask pattern is generated using the first group boundary.
US09286433B2
A computer implemented method for forming an integrated circuit (IC) layout is presented. The method includes forming a constraint tree when a computer is invoked to receive a first layout of the IC and generating a second layout of the IC in accordance with the constraint tree.
US09286413B1
One or more processing devices cause display of a service-monitoring dashboard that includes one or more key performance indicator (KPI) widgets. Each KPI widget provides a numerical or graphical representation of one or more values for a corresponding KPI indicating how a service provided by one or more entities is performing at one or more points in time. Each entity of the one or more entities is associated with machine data. A KPI is defined by a search query that derives the one or more values represented by the corresponding KPI widget from the machine data associated with the one or more entities that provide the service whose performance is reflected by the KPI.
US09286410B2
An approach is provided for retrieving electronic documents. The approach provides a Web-based graphical user interface that allows users to construct complex queries that include Boolean clauses, proximity clauses and/or keyword phrases, without requiring the users to have a working knowledge of query languages. The Web-based graphical user interface also allows users to specify a semantic meaning for one or more search terms. The approach also allows users to generate various reports for search results. Various filters may be applied to manage the amount of reporting data and semantic meanings may be applied to increase relevancy. A time cost estimator provides an estimated review time for search results.
US09286407B2
A method of bookmarking internet resources in an internet browser includes providing to a user an internet resource discovered by a search conducted via the browser in accordance with user supplied criteria; creating, responsive to a bookmarking request from the user, bookmark data having identifying data for the internet resource and an associated resource representation of the internet resource; and creating a hierarchy, for presentation to the user, of representations of internet resources for which bookmarking has been requested and of associated search criteria, each bookmarked resource representation being placed subordinate to corresponding associated search criteria representation in the hierarchy. A user can navigate to a bookmarked representation of a resource of interest via the corresponding associated search criteria representation for selection and subsequent retrieval of the resource of interest.
US09286406B2
A unique ID generation apparatus that may generate a unique ID of a radio frequency (RE) card includes a card recognition unit that recognizes an RF card; a command transmission unit that transmits, to the recognized RF card, a plurality of commands which respectively correspond to a plurality of RF protocols; a response reception unit that receives, from the RF card, responses to one or more of the plurality of commands; and a unique ID generation unit that generates a unique ID of the RF card based on the received responses.
US09286405B2
Methods, systems, and apparatus, including computer programs encoded on computer storage media, for index-side synonym expansion are disclosed. Some implementations include actions of obtaining a token sequence for a resource, wherein each token in the token sequence comprises one or more characters. The actions also include selecting a token from the token sequence, wherein the selected token comprises at least one numeric portion having one or more contiguous numeric characters, and at least one non-numeric portion having one or more non-numeric characters. Further actions include generating a new token corresponding to each of the at least one numeric portions of the selected token and storing data associating the selected token and each of the new tokens corresponding to the at least one numeric portion of the selected token as index terms for the resource, wherein the search engine index is accessed to augment search queries.
US09286402B2
A system for determining whether a website is an illegitimate website, the system comprising: a requester module configured to request one or more rules from a host server for a website and to receive a response from the host server in response to a request; an analysis module configured to determine whether a response or lack of a response received by the requester module indicates that the website is an illegitimate website; and a record module configured to store an indication that the website is an illegitimate website, wherein the one or more rules provide one or more instructions to a robot computer program regarding access of the website by the robot computer program.
US09286400B2
In some embodiments, a method comprises detecting a request to display a tag cloud, where the tag cloud includes a plurality of tags and the tags hyperlink to related web content. The method can also comprise determining a user's interests and preferences based on the information provided by the user. The method can include using the information to determine the tags relevant to the user's preferences and interests. The method can also include displaying the tags in the tag cloud.
US09286394B2
An apparatus for assessing and controlling the quality of a project in a production environment is provided. The apparatus is configured to: receive a first score, wherein the first score comprises a first numerical value associated with a first level of quality, wherein the first level of quality is associated with a first deliverable; receive a second score, wherein the second score comprises a second numerical value associated with a second level of quality, wherein the second level of quality is associated with the first deliverable; and process the first score and the second score to generate a third score.
US09286392B2
The present invention provides methods, devices, and systems for displaying results of a search engine query in a graphic, rather than, or in addition to, textual format. The search results are provided to a user such that the user is able to see the context of the words and phrases in the format of the original source document. Presentation of graphic fragments from the source document help to improve a user's ability to select among documents provided in the search results more efficiently.
US09286384B2
Methods and apparatus to share file(s)/recommendation(s) are disclosed. An example method includes verifying a first service used by a first user recommending a file and encoding a first service identification code with the file based on the first service, verifying a second service used by a second user upon receipt of a file request by the second user and/or detection of a mention of the second user in the file recommendation, searching for a second service identification code associated with the file based on the second service and encoding the second service identification code with the file, and providing the file recommendation with the first service identification code to the second user where the second service and the first service are the same or providing the file recommendation with the second service identification code to the second user where the second service and the first service are different.
US09286381B2
A disjoint partial-area taxonomy abstraction network and methods of producing same for a hierarchy, which partitions overlapping concepts into singly-rooted disjoint groups that are more manageable to work with and comprehend. This provides abstract models for summarizing overlapping concepts which permit enhanced, high-level display for users at a user interface.
US09286379B2
Systems and methods are disclosed herein for ranking the quality of documents, such as documents shared or referenced in postings by users. For a first set of documents quality attributes that are indicative of quality or lack of quality are identified. Ratings of the quality of the first set of documents are received. Classifiers are associated with each document and the ratings and quality attributes for each attribute used to train class-specific models corresponding to the classifiers. Subsequently received documents are then classified and corresponding quality attributes are evaluated using the corresponding class-specific model in order to rank the quality of the document.
US09286370B2
Techniques are disclosed for generating a dimensional query that includes dimensional and relational constructs. A report specification for retrieving data from a dimensional data model is received. The report specification includes the dimensional and relational constructs. The dimensional query is generated from the report specification, based on a predetermined sequence of applying the dimensional and relational constructs.
US09286366B2
In one embodiment, an apparatus includes a processor and logic integrated with and/or executable by the processor configured to cause the processor to receive data to store to a first cluster, store one or more copies of the data to the first cluster, and set a time-delayed copy consistency point time-delayed cops consistency point indicating an amount of time in which data stored to the first cluster is aged prior to being copied from the first cluster to a second cluster. In another embodiment, a method for time-delayed replication includes receiving data to store to a first cluster, storing one or more copies of the data to the first cluster, and setting a time-delayed copy consistency point, the time-delayed copy consistency point indicating an amount of time in which data stored to the first cluster is aged prior to being copied from the first cluster to a second cluster.
US09286365B2
A data synchronizing system and a method thereof are provided. One of clients capable of being connected to a synchronizing server may be selected as a synchronization processing client, and after the synchronization processing client is synchronized with all the clients, the synchronization processing client is synchronized with the synchronizing server, so as to achieve the technical efficacy of improving synchronizing convenience of a plurality of clients.
US09286363B2
A facility for navigating within a body of data using one of a number of distinct browse graphs is described. Initially, a navigation request is received. Based upon information contained in the received navigation request, the facility selects one of the plurality of browse graphs. In response to user input, the facility browses the body of data using the selected browse graph. The browse graphs may each correspond to a collection of the body of data, such as a website.
US09286348B2
A method is described of dynamically searching a search domain. A first result set of data objects is presented. The first result set is obtained from a first search of a search domain having active and inactive data objects for first search features obtained from a source data object. An update is detected in the search domain. Key features are extracted from the source data object to be included in second search features when the update in the search domain is in the source data object. A second search of the updated search domain is performed for data objects having the second search features.
US09286347B2
Improved descriptive query techniques are provided. More particularly, techniques are provided for specifying and processing descriptive queries for data providers grouped into provider kinds with hierarchical containment relationships. The query may include arbitrary boolean combinations of arbitrary tests on the values of attributes of the data providers.
US09286341B2
A database comprises a database interface and a database updater. The database interface enables a reading of a first set of information from the database. The database updater updates a second set of information in the database based at least in part on one or more conditions. The one or more conditions limit changes allowable to the first set of information from the database that occurred after the reading of the first set of information from the database.
US09286340B2
Systems and methods for collecting information from digital media files. More specifically, a collection module may be used to communicate with a social networking system and analyze the digital media files associated with a user profile. The collection module may generate media-based profile information based on media content and/or location, time and date data extracted from the digital media files. The media-based profile information may be incorporated into the user profile information and used by the social networking system for various purposes.
US09286339B2
A method for dynamically partitioning a B-tree data structure, includes: determining if the B-tree data structure requires a partition; establishing a midpoint of the B-tree data structure; migrating from a beginning of the B-tree data structure to the midpoint of the B-tree data structure to a first B-tree data structure; migrating from the midpoint of the B-tree data structure to an end of the B-tree data structure to a second B-tree data structure; and allowing normal operations on the B-tree data structure during migration.
US09286326B1
A system for selecting an image to accompany text from a user in connection with a social media post. The system includes receiving text from the user; identifying one or more search terms based on the text; identifying candidate images from images in one or more image databases using the search terms, where the candidate images comprise a sponsored image; presenting one or more candidate images to the user, where the sponsored image is presented preferentially compared to other candidate images; receiving from the user a selected image from the one or more candidate images; generating the social media post comprising the selected image and the user-submitted text; and transmitting the social media post for display.
US09286312B2
An approach to compression of a large (n point or samples) data set has a combination of one or more desirable technical properties: for a desired level of accuracy (ε), the number of compressed points (a “coreset”) representing the original data is O(log n); the level of accuracy comprises a guaranteed bound expressed as multiple of error of an associated line simplification of the data set; for a desired level of accuracy and a complexity (e.g., number k of optimal line segments) of the associated line simplification, the computation time is O(n); and for a desired level of accuracy (c) and a complexity of the associated line simplification, the storage required for the computation is O(log n).
US09286311B2
This technology relates to real-time filtering of relevant events from a plurality of events distributed spatially. An event processing engine receives the plurality of events from one or more real-time data sources. The received plurality of events are each compared with significant events stored in a significant event database and an entity associated with each of the significant events is identified. Next, the event processing engine identifies related events associated with each of the identified entities. The related events are aggregated to form one or more temporal sequence structures which are then matched with a plurality of sequential event patterns to identify each of the temporal sequence structures which match at least one of the plurality sequential event patterns. The entity associated with the one or more temporal sequence structures is filtered for providing one or more actions.
US09286303B1
A catalog of one or more metadata objects associated with metadata is stored in a persistent manner. The data objects are stored at least in part on a user node included in a data management system. A request associated with accessing a metadata object included in the persistent catalog is received. In response to receiving the request, access to the requested metadata object is provided.
US09286302B2
Systems and methods for inode use are presented. In one embodiment; an inode reuse method includes: receiving an indication of an operation that involves access to file related information; assigning an inode to the access; identifying one of a plurality of inode reuse scenarios for the inode; and making the inode available for reuse in accordance with the one of the plurality of inode reuse scenarios. In one embodiment, the one of the plurality of inode reuse scenarios is a relatively expedited reuse scenario. In one exemplary implementation, the relatively expedited inode reuse scenario is utilized if the inode is not required for further processing associated with the operation. The inode can be reused for another immediately subsequent operation. In one embodiment, a first one of the plurality of inode reuse scenarios includes placing the inode at a head queue position of a use queue and a second one of the plurality of inode reuse scenarios includes placing the inode in a tail queue position of the use queue. Association of the inode to the inode reuse scenario can be tracked. The tracking can include flagging the inode for relatively expedited reuse.
US09286290B2
Mechanisms for generating insight statements from table data are provided. A portion of content comprising a table data structure and text associated with the table data structure is received and at least one of key terms or semantic relationships in the table data structure and the associated text are identified. Fields of an insight statement template are populated with information obtained from the key terms and semantic relationships to generate an insight statement data structure. The insight statement data structure is then output. The insight statement data structure is a natural language statement describing an aspect of the table data structure.
US09286285B1
A computer-implemented method for editing a formula includes receiving a text string including formula information. The method further includes parsing the received text string and analyzing the parsed text string for a formula and formula errors while the text string is being received. In response to a formula error being detected in the analyzed text string, the method can include generating a message pertaining to the formula error. In response to a formula detected in the analyzed text string, the method can include calculating at least one sub-value for the formula and generating a message pertaining to the at least one sub-value of the formula.
US09286280B2
Classification and text analytics are used to evaluate passages, extract text, identify concepts, and provide displayable and searchable notations to assist document editors in identifying and evaluating conflicting or duplicate directives (also called policies or rules) within a large document.
US09286277B2
Inputting in a textbox comprises: monitoring a related event of inputting text in a textbox; providing an extended window for displaying excess text in response to detecting that the text exceeds the textbox; hiding the extended window, and storing a state of inputted context and the inputted text in response to a monitored event that the textbox loses focus; and displaying the extended window and the textbox, with their text, according to the stored state of inputted context in response to monitoring again the related event of inputting text in the textbox after monitoring the event that the textbox loses the focus. A global view can thus be provided for a user, whereby the user is capable of seeing at one time the content as a whole inputted by himself/herself, and immediately locating the last text inputted when the user leaves the textbox and then comes back for inputting.
US09286274B2
Methods and systems for enabling a user to define a webpage and webpage layout without knowing a programming language are disclosed. A library of modules is provided usable to configure a layout and look of a webpage. The user may add modules from the library to a webpage layout design area. The user may configure a given module so as to control the look and feel of the content accessed and displayed by the module. Different instantiations of the same module may be used to access content from different sources, including sources using different file and data formats. Content from the different sources may be accessed and stored in a schema-less database.
US09286269B2
An information processing device includes: a receiving unit; a discriminating unit; a plotting unit; a determining unit; a correcting unit; and a linear segment plotting unit.
US09286267B2
In one embodiment, the present invention includes a method for receiving a rounding instruction and an immediate value in a processor, determining if a rounding mode override indicator of the immediate value is active, and if so executing a rounding operation on a source operand in a floating point unit of the processor responsive to the rounding instruction and according to a rounding mode set forth in the immediate operand. Other embodiments are described and claimed.
US09286253B2
A method, system and computer readable medium for presenting unique Serial Attached Small computer system interface (SAS) target devices through a single target device. The method includes embedding a SAS protocol chip within an initiator-connectable device, the SAS protocol chip having storage for at least two SAS addresses and configured to select a single address, loading two or more SAS addresses into the SAS protocol chip, and mapping a respective SAS address to one of the unique target devices. The system includes a SAS protocol chip having storage for at least two SAS addresses and a method for selecting a single SAS address, and a processor unit connected to the SAS protocol chip by an interface bus, the processor configured to load two or more identifier addresses into the SAS protocol chip. The computer readable medium contains instructions that cause a processor to perform the described methods.
US09286250B2
There is a need to cause a delay to occur less frequently than the related art during processing of an input signal in need of relatively fast processing. In a semiconductor device, a conversion portion includes first channels and second channels and A/D converts a signal input to a selected channel. A signal input to the first channel requires faster processing than a signal input to the second channel. The conversion portion receives a scan conversion instruction from a central processing unit, sequentially selects the input channels in a specified selection order, and successively performs A/D conversion. In this case, the conversion portion notifies a peripheral circuit of completion of A/D conversion after completion of A/D conversion on signals input to the first channels and before completion of A/D conversion on input signals input to all input channels.