Invention Grant
- Patent Title: Power transistor die
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Application No.: US15631392Application Date: 2017-06-23
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Publication No.: US10083921B2Publication Date: 2018-09-25
- Inventor: Yu-Syuan Lin , Jiun-Lei Jerry Yu , Ming-Cheng Lin , Hsin-Chieh Huang , Chao-Hsiung Wang
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Eschweiler & Potashnik, LLC
- Main IPC: H01L29/00
- IPC: H01L29/00 ; H01L23/00 ; H01L23/58 ; H01L21/78 ; H01L29/20 ; H01L29/40 ; H01L29/778

Abstract:
Some embodiments relate to a die that has been formed by improved dicing techniques. The die includes a substrate which includes upper and lower substrate surfaces with a vertical substrate sidewall extending therebetween. The vertical substrate sidewall corresponds to an outermost edge of the substrate. A device layer is arranged over the upper substrate surface. A crack stop is arranged over an upper surface of the device layer and has an outer perimeter that is spaced apart laterally from the vertical substrate sidewall. The die exhibits a tapered sidewall extending downward through at least a portion of the device layer to meet the vertical substrate sidewall.
Public/Granted literature
- US20170294391A1 DICING TECHNIQUES FOR POWER TRANSISTORS Public/Granted day:2017-10-12
Information query
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