公开(公告)号：US12131911B2

公开(公告)日：2024-10-29

申请号：US17844563

申请日：2022-06-20

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Che-Lun Chang ,  Pin-Chuan Su ,  Hsin-Chieh Huang ,  Ming-Yuan Wu ,  Tzu kai Lin ,  Yu-Wen Wang ,  Che-Yuan Hsu

IPC分类号： H01L21/306 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/311 ,  H01L29/66

CPC分类号： H01L21/30625 ,  H01L21/02447 ,  H01L21/02532 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/31111 ,  H01L21/31116 ,  H01L29/66636

摘要： A method of forming a semiconductor device includes forming a first epitaxial layer over a substrate to form a wafer, depositing a dielectric layer over the first epitaxial layer, patterning the dielectric layer to form an opening, etching the first epitaxial layer through the opening to form a recess, forming a second epitaxial layer in the recess, etching the dielectric layer to expose a top surface of the first epitaxial layer, and planarizing the exposed top surface of the first epitaxial layer and a top surface of the second epitaxial layer.

公开(公告)号：US20230361181A1

公开(公告)日：2023-11-09

申请号：US18353498

申请日：2023-07-17

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chia-Ming Chang ,  Chi-Wen Liu ,  Cheng-Chien Li ,  Hsin-Chieh Huang

IPC分类号： H01L29/36 ,  H01L29/167 ,  H01L29/06 ,  H01L29/78 ,  H01L21/265 ,  H01L21/02 ,  H01L29/417 ,  H01L29/66

CPC分类号： H01L29/36 ,  H01L29/167 ,  H01L29/0657 ,  H01L29/785 ,  H01L21/26506 ,  H01L21/02532 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7848

摘要： A semiconductor device includes a substrate, at least one semiconductor fin, and at least one epitaxy structure. The semiconductor fin is present on the substrate. The semiconductor fin has at least one recess thereon. The epitaxy structure is present in the recess of the semiconductor fin. The epitaxy structure includes a topmost portion, a first portion and a second portion arranged along a direction from the semiconductor fin to the substrate. The first portion has a germanium atomic percentage higher than a germanium atomic percentage of the topmost portion and a germanium atomic percentage of the second portion.

公开(公告)号：US20220262926A1

公开(公告)日：2022-08-18

申请号：US17728633

申请日：2022-04-25

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Che-Lun Chang ,  Shiao-Shin Cheng ,  Ji-Yin Tsai ,  Yu-Lin Tsai ,  Hsin-Chieh Huang ,  Ming-Yuan Wu ,  Jiun-Ming Kuo ,  Ming-Jie Huang ,  Yu-Wen Wang ,  Che-Yuan Hsu

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L29/78 ,  H01L29/165 ,  H01L29/08

摘要： A method includes forming a doped region on a top portion of a substrate, forming a first epitaxial layer over the substrate, forming a recess in the first epitaxial layer, the recess being aligned to the doped region, performing a surface clean treatment in the recess, the surface clean treatment includes: oxidizing surfaces of the recess to form an oxide layer in the recess, and removing the oxide layer from the surfaces of the recess, and forming a second epitaxial layer in the recess.

公开(公告)号：US20190252323A1

公开(公告)日：2019-08-15

申请号：US16396794

申请日：2019-04-29

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ming-Yen Chiu ,  Ching-Fu Chang ,  Hsin-Chieh Huang

IPC分类号： H01L23/538 ,  H01L23/31 ,  H01L49/02 ,  H01L21/683 ,  H01L23/66

摘要： An integrated fan-out package including an integrated circuit, an insulating encapsulation, and a redistribution circuit structure is provided. The integrated circuit includes an antenna region. The insulating encapsulation encapsulates the integrated circuit. The redistribution circuit structure is disposed on the integrated circuit and the insulating encapsulation. The redistribution circuit structure is electrically connected to the integrated circuit, and the redistribution circuit structure includes a redistribution region and a dummy region including a plurality of dummy patterns embedded therein, wherein the antenna region includes an inductor and a wiring-free dielectric portion, and the wiring-free dielectric portion of the antenna region is between the inductor and the dummy region.

公开(公告)号：US10326006B2

公开(公告)日：2019-06-18

申请号：US16229026

申请日：2018-12-21

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yen-Ming Peng ,  Chi-Wen Liu ,  Hsin-Chieh Huang ,  Yi-Ju Hsu ,  Horng-Huei Tseng

IPC分类号： H01L21/70 ,  H01L29/66 ,  H01L29/78

摘要： A FinFET device includes a substrate, a fin formed on the substrate, and a gate electrode crossing the fin. The gate electrode includes a head portion and a tail portion, and the tail portion is connected to the head portion and extended toward the substrate. The width of the head portion is greater than that of the tail portion.

公开(公告)号：US10276506B2

公开(公告)日：2019-04-30

申请号：US15215594

申请日：2016-07-21

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ming-Yen Chiu ,  Ching-Fu Chang ,  Hsin-Chieh Huang

IPC分类号： H01L23/538 ,  H01L49/02 ,  H01L23/66 ,  H01L23/31

摘要： A semiconductor device including an integrated circuit, a protection layer, and a conductive via is provided. The integrated circuit includes at least one conductive pad. The protection layer covers the integrated circuit. The protection layer includes a contact opening, and the conductive pad is exposed by the contact opening of the protection layer. The conductive via is embedded in the contact opening of the protection layer, and the conductive via is electrically connected to the conductive pad through the contact opening. A method of fabricating the above-mentioned semiconductor device and an integrated fan-out package including the above-mentioned semiconductor device are also provided.

公开(公告)号：US10037961B2

公开(公告)日：2018-07-31

申请号：US15156339

申请日：2016-05-17

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ming-Yen Chiu ,  Ching-Fu Chang ,  Hsin-Chieh Huang

IPC分类号： H01L23/00 ,  H01L23/48 ,  H01L23/544 ,  H01L23/31 ,  H01L21/768 ,  H01L21/56 ,  H01L21/3105 ,  H01L21/683 ,  H01L25/065 ,  H01L21/78

CPC分类号： H01L24/14 ,  H01L21/31053 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76885 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3192 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/5389 ,  H01L23/544 ,  H01L24/06 ,  H01L24/20 ,  H01L25/0657 ,  H01L2221/68327 ,  H01L2221/68359 ,  H01L2224/0231 ,  H01L2224/0237 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/13014 ,  H01L2224/13016 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/059 ,  H01L2924/06 ,  H01L2924/07025 ,  H01L2924/14 ,  H01L2224/03 ,  H01L2924/014

摘要： An integrated fan-out package including an integrated circuit, an insulating encapsulation, a plurality of conductive through vias, and a redistribution circuit structure is provided. The integrated circuit includes a plurality of conductive terminals. The insulating encapsulation encapsulates sidewalls of the integrated circuit. The conductive through vias penetrate in the insulating encapsulation. The redistribution circuit structure is disposed on the integrated circuit, the conductive through vias and the insulating encapsulation. The redistribution conductive layer is electrically connected to the conductive terminals and the conductive through vias. A plurality of first contact surfaces of the conductive terminals and a plurality of second contact surfaces of the conductive through vias are in contact with the redistribution circuit structure, and a roughness of the first contact surfaces and the second contact surfaces ranges from 100 angstroms to 500 angstroms. Methods of fabricating the integrated fan-out package are also provided.

公开(公告)号：US09941216B2

公开(公告)日：2018-04-10

申请号：US15281043

申请日：2016-09-29

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ming-Yen Chiu ,  Ching-Fu Chang ,  Chien-Chia Chiu ,  Hsin-Chieh Huang ,  Tsung-Shu Lin ,  Pei-Ti Yu

IPC分类号： H01L23/538 ,  H01L25/10

CPC分类号： H01L23/5386 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/568 ,  H01L23/49811 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311

摘要： A conductive pattern including a teardrop shaped portion, a routing line, and a connection portion is provided. The routing line links to the teardrop shaped portion through the connection portion, and a width of the connection portion decreases along an extending direction from the teardrop shaped portion to the routing line. Furthermore, an integrated fan-out package including the above-mentioned conductive pattern is also provided.

公开(公告)号：US20170294391A1

公开(公告)日：2017-10-12

申请号：US15631392

申请日：2017-06-23

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yu-Syuan Lin ,  Jiun-Lei Jerry Yu ,  Ming-Cheng Lin ,  Hsin-Chieh Huang ,  Chao-Hsiung Wang

IPC分类号： H01L23/58 ,  H01L29/778 ,  H01L29/40 ,  H01L21/78 ,  H01L29/20

CPC分类号： H01L23/585 ,  H01L21/78 ,  H01L21/784 ,  H01L23/5226 ,  H01L23/562 ,  H01L29/0657 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/7786 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： Some embodiments relate to a die that has been formed by improved dicing techniques. The die includes a substrate which includes upper and lower substrate surfaces with a vertical substrate sidewall extending therebetween. The vertical substrate sidewall corresponds to an outermost edge of the substrate. A device layer is arranged over the upper substrate surface. A crack stop is arranged over an upper surface of the device layer and has an outer perimeter that is spaced apart laterally from the vertical substrate sidewall. The die exhibits a tapered sidewall extending downward through at least a portion of the device layer to meet the vertical substrate sidewall.

公开(公告)号：US20170069757A1

公开(公告)日：2017-03-09

申请号：US14994057

申请日：2016-01-12

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Yen-Ming Peng ,  Chi-Wen Liu ,  Hsin-Chieh Huang ,  Yi-Ju Hsu ,  Horng-Huei Tseng

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/49 ,  H01L29/423

CPC分类号： H01L29/66795 ,  H01L29/7848 ,  H01L29/785

摘要： A FinFET device includes a substrate, a fin formed on the substrate, and a gate electrode crossing the fin. The gate electrode includes a head portion and a tail portion, and the tail portion is connected to the head portion and extended toward the substrate. The width of the head portion is greater than that of the tail portion.

摘要翻译： FinFET器件包括衬底，形成在衬底上的鳍片和与鳍片交叉的栅极电极。 栅电极包括头部和尾部，尾部连接到头部并朝向衬底延伸。 头部的宽度大于尾部的宽度。