中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

9 records (took 0.015 seconds)

    Integrated ESD Protection Circuit for GaN Based Device
    1.
    发明申请
    Integrated ESD Protection Circuit for GaN Based Device 审中-公开

    公开(公告)号：US20180026029A1

    公开(公告)日：2018-01-25

    申请号：US15215651

    申请日：2016-07-21

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yu-Syuan Lin ,  Ming-Cheng Lin ,  King-Yuen Wong ,  Jiun-Lei Yu ,  Chun Lin Tsai

    IPC: H01L27/02 ,  H01L49/02 ,  H01L27/06 ,  H01L29/20 ,  H01L29/778

    CPC classification number: H01L28/20 ,  H01L27/0248 ,  H01L27/0605

    Abstract: The present disclosure relates to an electrostatic discharge (ESD) protection circuit integrated with a gallium nitride (GaN) based transistor and configured to clamp a gate input voltage of the gallium nitride (GaN) based transistor during an ESD surge event, and associated methods. In some embodiments, the ESD protection circuit includes a first ESD protection stage and a second ESD protection stage connected between a gate terminal and a source terminal of the GaN based transistor. The first ESD protection stage includes a first plurality of GaN based gate-to-source shorted transistors connected in series and further connected to a first terminal of a first resistor. The second ESD protection stage is connected to the first ESD protection stage in parallel. The second ESD protection stage comprises a first GaN based shunt transistor having a gate terminal connected to the first terminal of the first resistor.

    HEMT-COMPATIBLE LATERAL RECTIFIER STRUCTURE
    3.
    发明申请
    HEMT-COMPATIBLE LATERAL RECTIFIER STRUCTURE 有权
    HEMT兼容的横向整流器结构

    公开(公告)号：US20150034958A1

    公开(公告)日：2015-02-05

    申请号：US13956902

    申请日：2013-08-01

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： King-Yuen Wong ,  Yu-Syuan Lin ,  Chih-Wen Hsiung

    IPC: H01L29/20 ,  H01L29/66 ,  H01L29/778

    CPC classification number: H01L29/2003 ,  H01L29/66462 ,  H01L29/7787 ,  H01L29/861

    Abstract: The present disclosure relates to a high electron mobility transistor compatible power lateral field-effect rectifier device. In some embodiments, the rectifier device has an electron supply layer located over a layer of semiconductor material at a position between an anode terminal and a cathode terminal. A layer of doped III-N semiconductor material is disposed over the electron supply layer. A layer of gate isolation material is located over the layer of doped III-N semiconductor material. A gate structure is disposed over layer of gate isolation material, such that the gate structure is separated from the electron supply layer by the layer of gate isolation material and the layer of doped III-N semiconductor material. The layer of doped III-N semiconductor material modulates the threshold voltage of the rectifier device, while the layer of gate isolation material provides a barrier that gives the rectifier device a low leakage.

    Abstract translation: 本公开涉及一种高电子迁移率晶体管兼容功率侧向场效应整流器件。 在一些实施例中，整流器件在阳极端子和阴极端子之间的位置具有位于半导体材料层上方的电子供应层。 掺杂的III-N半导体材料层设置在电子供应层上。 一层栅极隔离材料位于掺杂的III-N半导体材料的层上。 栅极结构设置在栅极隔离材料的层上，使得栅极结构通过栅极隔离材料层和掺杂的III-N半导体材料层与电子供应层分离。 掺杂的III-N半导体材料的层调制整流器件的阈值电压，而栅极隔离材料层提供了使整流器件具有低泄漏的势垒。

    HEMT-compatible lateral rectifier structure
    5.
    发明授权
    HEMT-compatible lateral rectifier structure 有权

    公开(公告)号：US09806158B2

    公开(公告)日：2017-10-31

    申请号：US13956902

    申请日：2013-08-01

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： King-Yuen Wong ,  Yu-Syuan Lin ,  Chih-Wen Hsiung

    IPC: H01L29/20 ,  H01L29/66 ,  H01L29/778 ,  H01L29/861

    CPC classification number: H01L29/2003 ,  H01L29/66462 ,  H01L29/7787 ,  H01L29/861

    Abstract: The present disclosure relates to a high electron mobility transistor compatible power lateral field-effect rectifier device. In some embodiments, the rectifier device has an electron supply layer located over a layer of semiconductor material at a position between an anode terminal and a cathode terminal. A layer of doped III-N semiconductor material is disposed over the electron supply layer. A layer of gate isolation material is located over the layer of doped III-N semiconductor material. A gate structure is disposed over layer of gate isolation material, such that the gate structure is separated from the electron supply layer by the layer of gate isolation material and the layer of doped III-N semiconductor material. The layer of doped III-N semiconductor material modulates the threshold voltage of the rectifier device, while the layer of gate isolation material provides a barrier that gives the rectifier device a low leakage.

    DICING METHOD FOR POWER TRANSISTORS
    9.
    发明申请
    DICING METHOD FOR POWER TRANSISTORS 有权
    功率晶体管的定义方法

    公开(公告)号：US20160204074A1

    公开(公告)日：2016-07-14

    申请号：US14596326

    申请日：2015-01-14

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yu-Syuan Lin ,  Jiun-Lei Jerry Yu ,  Ming-Cheng Lin ,  Hsin-Chieh Huang ,  Chao-Hsiung Wang

    IPC: H01L23/00 ,  H01L23/522 ,  H01L23/58 ,  H01L29/20 ,  H01L29/78

    CPC classification number: H01L23/585 ,  H01L21/78 ,  H01L21/784 ,  H01L23/5226 ,  H01L23/562 ,  H01L29/0657 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/7786 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Some embodiments relate to a method of dicing a semiconductor wafer. The semiconductor wafer that includes a device structure that is formed within a device layer. The device layer is arranged within an upper surface the device layer. A crack stop is formed, which surrounds the device structure and reinforces the semiconductor wafer to prevent cracking during dicing. A laser is used to form a groove along a scribe line outside the crack stop. The groove extends completely through the device layer, and into an upper surface region of the semiconductor wafer. The semiconductor wafer is then cut along the grooved scribe line with a cutting blade to singulate the semiconductor wafer into two or more die. By extending the groove completely through the device layer, the method avoids damage to the device layer caused by the blade saw, and thus avoids an associated performance degradation of the device structure.

    Abstract translation: 一些实施例涉及切割半导体晶片的方法。 该半导体晶片包括在器件层内形成的器件结构。 器件层布置在器件层的上表面内。 形成裂缝停止件，其围绕装置结构并加强半导体晶片以防止切割期间的开裂。 使用激光器沿着裂纹停止点外的划线形成凹槽。 凹槽完全延伸穿过器件层并进入半导体晶片的上表面区域。 然后用切割刀沿着带槽划线切割半导体晶片，将半导体晶片分成两个或更多个管芯。 通过将槽完全延伸穿过器件层，该方法避免了由刀片锯引起的对器件层的损坏，从而避免了器件结构的相关性能下降。

Patent Agency Ranking