Invention Grant
- Patent Title: Memory devices and systems having reduced bit line to drain select gate shorting and associated methods
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Application No.: US15683672Application Date: 2017-08-22
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Publication No.: US10134758B2Publication Date: 2018-11-20
- Inventor: Hongbin Zhu , Jun Zhao , Purnima Narayanan , Gordon Haller , Damir Fazil
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Thorpe North & Western, LLP
- Agent David W. Osborne
- Main IPC: H01L27/11582
- IPC: H01L27/11582 ; G11C16/04 ; G11C16/08 ; G11C16/10 ; G11C16/24 ; G11C16/26 ; H01L21/768 ; H01L27/1157
Abstract:
3D NAND memory devices and systems having reduced bit line to drain select gate shorting, including associated methods, are provided and described.
Public/Granted literature
- US20180130819A1 MEMORY DEVICES AND SYSTEMS HAVING REDUCED BIT LINE TO DRAIN SELECT GATE SHORTING AND ASSOCIATED METHODS Public/Granted day:2018-05-10
Information query
IPC分类:
