公开(公告)号：US20180130819A1

公开(公告)日：2018-05-10

申请号：US15683672

申请日：2017-08-22

Applicant: Intel Corporation

Inventor： Hongbin Zhu ,  Jun Zhao ,  Purnima Narayanan ,  Gordon Haller ,  Damir Fazil

IPC: H01L27/11582 ,  H01L27/1157 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  H01L21/768 ,  G11C16/24

CPC classification number: H01L27/11582 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76897 ,  H01L27/1157

Abstract: 3D NAND memory devices and systems having reduced bit line to drain select gate shorting, including associated methods, are provided and described.

公开(公告)号：US09741734B2

公开(公告)日：2017-08-22

申请号：US14970288

申请日：2015-12-15

Applicant: Intel Corporation

Inventor： Hongbin Zhu ,  Jun Zhao ,  Purnima Narayanan ,  Gordon Haller ,  Damir Fazil

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L21/768 ,  G11C16/04 ,  G11C16/08 ,  G11C16/26 ,  G11C16/24 ,  G11C16/10

CPC classification number: H01L27/11582 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76897 ,  H01L27/1157

Abstract: 3D NAND memory devices and systems having reduced bit line to drain select gate shorting, including associated methods, are provided and described.

公开(公告)号：US10790290B2

公开(公告)日：2020-09-29

申请号：US15721224

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： David A. Daycock ,  Purnima Narayanan ,  John Hopkins ,  Guoxing Duan ,  Barbara L. Casey ,  Christopher J. Larsen ,  Meng-Wei Kuo ,  Qian Tao

IPC: H01L27/11524 ,  H01L27/1157 ,  H01L21/8234 ,  H01L27/11582 ,  H01L27/11556

Abstract: A 3D NAND storage device includes a plurality of layers containing doped semiconductor material interleaved with a plurality of layers of dielectric material. Each of the pillars forming the 3D NAND storage device includes a plurality of memory cells and a drain-end select gate (SGD). The pillars are separated by a hollow channel in which a plurality of film layers, including at least a lower film layer and an upper film layer have been deposited. The systems and methods described herein remove at least the upper film layer proximate the SGD while maintaining the film layers proximate the memory cells. Such an arrangement beneficially permits tailoring the film layers proximate the SGD prior to depositing the channel film layer in the hollow channel. The systems and methods described herein permit the deposition of a continuous channel film layer proximate both the memory cells and the SGD.

公开(公告)号：US20170170190A1

公开(公告)日：2017-06-15

申请号：US14970288

申请日：2015-12-15

Applicant: Intel Corporation

Inventor： Hongbin Zhu ,  Jun Zhao ,  Purnima Narayanan ,  Gordon Haller ,  Damir Fazil

IPC: H01L27/115 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/24 ,  H01L21/768 ,  G11C16/08

CPC classification number: H01L27/11582 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76897 ,  H01L27/1157

Abstract: 3D NAND memory devices and systems having reduced bit line to drain select gate shorting, including associated methods, are provided and described.

公开(公告)号：US10134758B2

公开(公告)日：2018-11-20

申请号：US15683672

申请日：2017-08-22

Applicant: Intel Corporation

Inventor： Hongbin Zhu ,  Jun Zhao ,  Purnima Narayanan ,  Gordon Haller ,  Damir Fazil

IPC: H01L27/11582 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  H01L21/768 ,  H01L27/1157

Abstract: 3D NAND memory devices and systems having reduced bit line to drain select gate shorting, including associated methods, are provided and described.