Invention Grant
- Patent Title: Methods and systems to control power gates during an active state of a gated domain based on load conditions of the gated domain
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Application No.: US14350548Application Date: 2011-12-27
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Publication No.: US10228738B2Publication Date: 2019-03-12
- Inventor: Michael Zelikson , Vjekoslav Svilan , Norbert Unger , Shai Rotem
- Applicant: Michael Zelikson , Vjekoslav Svilan , Norbert Unger , Shai Rotem
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Green, Howard & Mughal LLP
- International Application: PCT/US2011/067334 WO 20111227
- International Announcement: WO2013/100890 WO 20130704
- Main IPC: G06F1/00
- IPC: G06F1/00 ; G06F1/26 ; H03K17/687 ; G06F1/3234 ; G06F1/3287

Abstract:
Methods and systems to adjust a resistance between a supply grid and a power-gated grid during an active state of a power-gated circuitry in response to load changes in the circuitry to maintain a relatively consistent IR droop. Subsets of power gates (PGs) may be selectively enabled and disabled based on changes in a load factor, such as a voltage, which may be monitored at a gated power distribution grid and/or proximate to a transistor gate within the power-gated circuitry. The adjusting may be performed to minimize a difference between the monitored voltage and a reference, such as with successive approximation or CMS software. PG subsets may be distributed within one or more layers of an integrated circuit (IC) die and may be selectively enabled/disabled based on location. PGs may be embedded within lower layers of an integrated circuit (IC) die, such as within metal layers of the IC die.
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