公开(公告)号：US09037255B2

公开(公告)日：2015-05-19

申请号：US11721530

申请日：2005-12-09

申请人： Andre Rocke ,  Maurits Ortmanns ,  Norbert Unger

发明人： Andre Rocke ,  Maurits Ortmanns ,  Norbert Unger

IPC分类号： A61N1/00 ,  A61N1/08 ,  A61N1/36

CPC分类号： A61N1/36046 ,  A61N1/025 ,  A61N1/0543 ,  A61N1/08 ,  A61N1/36014 ,  A61N1/36128

摘要： A device for stimulating living tissue or nerves by individual or repeated stimulating pulses via stimulating electrodes which stimulate living tissue or nerves by stimulating pulses includes an electrical circuit which regulates the electric voltage or charge on the stimulating electrodes as a function of the electric voltage between the stimulating electrodes and reduces or equalises imbalances of electric charges on the stimulating electrodes. This device is capable of equalizing the electric charge on the stimulating electrodes of a stimulation system. The device and the process for using the device have the advantage that imbalances of electric charges on the stimulating electrodes, and the associated disadvantageous effects on the tissue and on the nerves, are avoided or eliminated. Furthermore, the device has a small space requirement.

摘要翻译： 通过刺激脉冲刺激活体组织或神经的刺激电极，通过个体或反复刺激脉冲刺激活组织或神经的装置包括调节刺激电极上的电压或电荷的电路， 刺激电极并且减小或均衡刺激电极上的电荷的不平衡。 该装置能够均衡刺激系统的刺激电极上的电荷。 该装置和使用该装置的方法具有避免或消除刺激电极上的电荷的不平衡以及对组织和神经的相关不利影响的优点。 此外，该设备具有小的空间要求。

公开(公告)号：US20150149794A1

公开(公告)日：2015-05-28

申请号：US14350548

申请日：2011-12-27

申请人： Michael Zelikson ,  Vjekoslav Svilan ,  Norbert Unger ,  Shai Rotem

发明人： Michael Zelikson ,  Vjekoslav Svilan ,  Norbert Unger ,  Shai Rotem

IPC分类号： G06F1/26 ,  H03K17/687

CPC分类号： G06F1/26 ,  G06F1/3243 ,  G06F1/3287 ,  H03K17/687 ,  Y02D10/152 ,  Y02D10/171

摘要： Methods and systems to adjust a resistance between a supply grid and a power-gated grid during an active state of a power-gated circuitry in response to load changes in the circuitry to maintain a relatively consistent IR droop. Subsets of power gates (PGs) may be selectively enabled and disabled based on changes in a load factor, such as a voltage, which may be monitored at a gated power distribution grid and/or proximate to a transistor gate within the power-gated circuitry. The adjusting may be performed to minimize a difference between the monitored voltage and a reference, such as with successive approximation or CMS software. PG subsets may be distributed within one or more layers of an integrated circuit (IC) die and may be selectively enabled/disabled based on location. PGs may be embedded within lower layers of an integrated circuit (IC) die, such as within metal layers of the IC die.

摘要翻译： 在电源选通电路的有效状态期间，响应于电路中的负载变化来调节电网和电网门控之间的电阻以维持相对一致的IR下降的方法和系统。 可以基于诸如电压的负载因子的变化来选择性地启用和禁用功率门（PG）的子集，其可以在门控配电网格处和/或接近电力门控电路中的晶体管栅极监视 。 可以执行调整以最小化所监视的电压和参考之间的差异，例如通过逐次逼近或CMS软件。 PG子集可以分布在集成电路（IC）裸片的一个或多个层内，并且可以基于位置被选择性地启用/禁用。 PG可以嵌入集成电路（IC）管芯的下层内，例如在IC管芯的金属层内。

公开(公告)号：US10228738B2

公开(公告)日：2019-03-12

申请号：US14350548

申请日：2011-12-27

申请人： Michael Zelikson ,  Vjekoslav Svilan ,  Norbert Unger ,  Shai Rotem

发明人： Michael Zelikson ,  Vjekoslav Svilan ,  Norbert Unger ,  Shai Rotem

IPC分类号： G06F1/00 ,  G06F1/26 ,  H03K17/687 ,  G06F1/3234 ,  G06F1/3287

摘要： Methods and systems to adjust a resistance between a supply grid and a power-gated grid during an active state of a power-gated circuitry in response to load changes in the circuitry to maintain a relatively consistent IR droop. Subsets of power gates (PGs) may be selectively enabled and disabled based on changes in a load factor, such as a voltage, which may be monitored at a gated power distribution grid and/or proximate to a transistor gate within the power-gated circuitry. The adjusting may be performed to minimize a difference between the monitored voltage and a reference, such as with successive approximation or CMS software. PG subsets may be distributed within one or more layers of an integrated circuit (IC) die and may be selectively enabled/disabled based on location. PGs may be embedded within lower layers of an integrated circuit (IC) die, such as within metal layers of the IC die.

公开(公告)号：US09966940B2

公开(公告)日：2018-05-08

申请号：US13976156

申请日：2011-09-23

申请人： Shai Rotem ,  Norbert Unger ,  Michael Zelikson

发明人： Shai Rotem ,  Norbert Unger ,  Michael Zelikson

IPC分类号： H03K17/00 ,  H03K17/687 ,  G06F1/32 ,  G06F1/26 ,  H03K19/00

CPC分类号： H03K17/00 ,  H03K17/687 ,  H03K2217/0036 ,  H03K2217/0063

摘要： A power-gate circuit includes a power-gate transistor operable to switch to decouple a first supply voltage from a second supply voltage during an idle mode, and to couple the first supply voltage to the second supply voltage during a full operational mode. Part of the charge stored at a gate terminal of the power-gate transistor, would have been otherwise flushed to ground while turning on the power-gate transistor, is routed to the rail of the second supply voltage of the logic block. Part of the charge on the rail of the second supply voltage is used to charge the gate terminal of the power-gate transistor to deactivate the power-gate transistor if the logic block goes to the idle mode. Energy is saved both ways because of the charge recycling and the ability to use the power gate circuit even in cases where the duration of the idle mode may be short.

公开(公告)号：US09594412B2

公开(公告)日：2017-03-14

申请号：US13996285

申请日：2012-03-30

申请人： Vjekoslav Svilan ,  Michael Zelikson ,  Kelvin Kwan ,  Naveen Neelakantam ,  Norbert Unger

发明人： Vjekoslav Svilan ,  Michael Zelikson ,  Kelvin Kwan ,  Naveen Neelakantam ,  Norbert Unger

IPC分类号： G06F1/00 ,  G06F1/26 ,  G06F1/32

CPC分类号： G06F1/26 ,  G06F1/3203 ,  G06F1/3287 ,  Y02D10/171

摘要： In one embodiment, the present invention includes an apparatus having an estimation logic to estimate a dynamic capacitance of a processor circuit of a processor during a plurality of processor cycles, a power gate calculator to calculate a control value for a power gate circuit coupled to a load line and between a voltage regulator and the processor circuit based on the dynamic capacitance estimate, and a controller to control an impedance of the power gate circuit based on the control value. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，本发明包括具有估计逻辑以在多个处理器周期期间估计处理器的处理器电路的动态电容的装置，功率门计算器，用于计算耦合到一个处理器周期的功率门电路的控制值 基于动态电容估计在负载线之间以及电压调节器和处理器电路之间，以及基于控制值来控制电源门电路的阻抗的控制器。 描述和要求保护其他实施例。

公开(公告)号：US20130275782A1

公开(公告)日：2013-10-17

申请号：US13996285

申请日：2012-03-30

申请人： Vjekoslav Svilan ,  Michael Zelikson ,  Kelvin Kwan ,  Naveen Neelakantam ,  Norbert Unger

发明人： Vjekoslav Svilan ,  Michael Zelikson ,  Kelvin Kwan ,  Naveen Neelakantam ,  Norbert Unger

IPC分类号： G06F1/26

CPC分类号： G06F1/26 ,  G06F1/3203 ,  G06F1/3287 ,  Y02D10/171

摘要： In one embodiment, the present invention includes an apparatus having an estimation logic to estimate a dynamic capacitance of a processor circuit of a processor during a plurality of processor cycles, a power gate calculator to calculate a control value for a power gate circuit coupled to a load line and between a voltage regulator and the processor circuit based on the dynamic capacitance estimate, and a controller to control an impedance of the power gate circuit based on the control value. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，本发明包括具有估计逻辑以在多个处理器周期期间估计处理器的处理器电路的动态电容的装置，功率门计算器，用于计算耦合到一个处理器周期的功率门电路的控制值 基于动态电容估计在负载线之间以及电压调节器和处理器电路之间，以及基于控制值来控制电源门电路的阻抗的控制器。 描述和要求保护其他实施例。

公开(公告)号：US20130293282A1

公开(公告)日：2013-11-07

申请号：US13976156

申请日：2011-09-23

申请人： Shai Rotem ,  Norbert Unger ,  Michael Zelikson

发明人： Shai Rotem ,  Norbert Unger ,  Michael Zelikson

IPC分类号： H03K17/00

CPC分类号： H03K17/00 ,  H03K17/687 ,  H03K2217/0036 ,  H03K2217/0063

摘要： A power-gate circuit includes a power-gate transistor operable to switch to decouple a first supply voltage from a second supply voltage during an idle mode, and to couple the first supply voltage to the second supply voltage during a full operational mode. Part of the charge stored at a gate terminal of the power-gate transistor, would have been otherwise flushed to ground while turning on the power-gate transistor, is routed to the rail of the second supply voltage of the logic block. Part of the charge on the rail of the second supply voltage is used to charge the gate terminal of the power-gate transistor to de-activate the power-gate transistor if the logic block goes to the idle mode. Energy is saved both ways because of the charge recycling and the ability to use the power gate circuit even in cases where the duration of the idle mode may be short.

摘要翻译： 电源门电路包括功率门晶体管，其可操作以切换以在空闲模式期间将第一电源电压与第二电源电压分离，并且在完全操作模式期间将第一电源电压耦合到第二电源电压。 存储在电源栅极晶体管的栅极端子处的电荷的一部分将被另外冲洗到地，同时导通电源栅极晶体管，被路由到逻辑块的第二电源电压的轨道。 如果逻辑块进入空闲模式，则使用第二电源电压的轨道上的电荷的一部分来对功率栅极晶体管的栅极端子进行充电以去激活功率栅极晶体管。 由于充电回收和即使在空闲模式的持续时间可能短的情况下使用电源门电路的能力也节省了能源。