Invention Grant
- Patent Title: Technologies for managing power during an activation cycle
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Application No.: US15484361Application Date: 2017-04-11
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Publication No.: US10261572B2Publication Date: 2019-04-16
- Inventor: Aswin Ramachandran , Arvind Raman
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Barnes & Thornburg LLP
- Main IPC: G06F1/32
- IPC: G06F1/32 ; G06F1/3287 ; G06F1/3296 ; G06F1/3228 ; G06F9/4401 ; G06F1/3203 ; G06F1/324 ; G06F11/07

Abstract:
Technologies of managing power during an activation cycle of a processor core or other compute domain include determining new operation limits for active processor cores or other compute domains during an activation cycle of a hibernating processor core or other hibernating compute domain to reduce the likelihood of a power surge during the activation of the hibernating processor core or other compute domain. The active processor cores or other compute domain are monitored until their operating points are at or below the new operating limits. Thereafter, the hibernating processor core or other hibernating compute domain is activated.
Public/Granted literature
- US20170220099A1 TECHNOLOGIES FOR MANAGING POWER DURING AN ACTIVATION CYCLE Public/Granted day:2017-08-03
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