Invention Grant
- Patent Title: 3D IC architecture with interposer and interconnect structure for bonding dies
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Application No.: US12774558Application Date: 2010-05-05
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Publication No.: US10297550B2Publication Date: 2019-05-21
- Inventor: Hsien-Pin Hu , Chen-Hua Yu , Ming-Fa Chen , Jing-Cheng Lin , Jiun Ren Lai , Yung-Chi Lin
- Applicant: Hsien-Pin Hu , Chen-Hua Yu , Ming-Fa Chen , Jing-Cheng Lin , Jiun Ren Lai , Yung-Chi Lin
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- Main IPC: H01L23/538
- IPC: H01L23/538 ; H01L23/488 ; H01L21/56 ; H01L21/683 ; H01L23/14 ; H01L23/31 ; H01L23/498 ; H01L23/00 ; H01L25/065

Abstract:
A device includes an interposer, which includes a substrate having a top surface. An interconnect structure is formed over the top surface of the substrate, wherein the interconnect structure includes at least one dielectric layer, and metal features in the at least one dielectric layer. A plurality of through-substrate vias (TSVs) is in the substrate and electrically coupled to the interconnect structure. A first die is over and bonded onto the interposer. A second die is bonded onto the interposer, wherein the second die is under the interconnect structure.
Public/Granted literature
- US20110193221A1 3DIC Architecture with Interposer for Bonding Dies Public/Granted day:2011-08-11
Information query
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