Invention Grant
- Patent Title: Multiple patterning method using mask portions to etch semiconductor substrate
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Application No.: US15833077Application Date: 2017-12-06
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Publication No.: US10347506B2Publication Date: 2019-07-09
- Inventor: Cheng-Li Fan , Chih-Hao Chen , Wen-Yen Chen
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Slater Matsil, LLP
- Main IPC: H01L21/311
- IPC: H01L21/311 ; H01L21/768
Abstract:
Methods for patterning in a semiconductor process are described. A dummy layer is formed having a cut therein. A first sacrificial layer is formed over the dummy layer, and at least a portion of the first sacrificial layer is disposed in the cut. A second sacrificial layer is formed over the first sacrificial layer. The second sacrificial layer is patterned to have a first pattern. Using the first pattern of the second sacrificial layer, the first sacrificial layer is patterned to have the first pattern. The second sacrificial layer is removed. Thereafter, a second pattern in the first sacrificial layer is formed comprising altering a dimension of the first pattern of the first sacrificial layer. Using the second pattern of the first sacrificial layer, the dummy layer is patterned. Mask portions are formed along respective sidewalls of the patterned dummy layer. The mask portions are used to form a mask.
Public/Granted literature
- US20190035638A1 MULTIPLE PATTERNING METHOD Public/Granted day:2019-01-31
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