Invention Grant
- Patent Title: Semiconductor package having a molding layer including a molding cavity and method of fabricating the same
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Application No.: US15960698Application Date: 2018-04-24
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Publication No.: US10361177B2Publication Date: 2019-07-23
- Inventor: Yun-Young Kim , Pyoungwan Kim , Hyunki Kim , Junwoo Park , Sangsoo Kim , Seung Hwan Kim , Sung-Kyu Park , Insup Shin
- Applicant: Samsung Electronics Co., Ltd.
- Applicant Address: KR Samsong-ro, Yeongtong-gu, Suwon-si, Gyeonggi-do
- Assignee: SAMSUNG ELECTRONICS CO., LTD
- Current Assignee: SAMSUNG ELECTRONICS CO., LTD
- Current Assignee Address: KR Samsong-ro, Yeongtong-gu, Suwon-si, Gyeonggi-do
- Agency: Muir Patent Law, PLLC
- Priority: KR10-2017-0108884 20170828
- Main IPC: H01L21/56
- IPC: H01L21/56 ; H01L25/00 ; H01L25/10 ; H01L25/11

Abstract:
Disclosed are a semiconductor package and a method of fabricating the same. The semiconductor package comprises a lower semiconductor chip on a lower substrate, a lower molding layer covering the lower semiconductor chip on the lower substrate and including a molding cavity that extends toward the lower semiconductor chip from a top surface of the lower molding layer, an interposer substrate on the top surface of the lower molding layer and including a substrate opening that penetrates the interposer substrate and overlaps the molding cavity, and an upper package on the interposer substrate. The molding cavity has a floor surface spaced apart from the upper package across a substantially hollow space.
Public/Granted literature
- US20190067258A1 SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME Public/Granted day:2019-02-28
Information query
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