公开(公告)号：US20230131730A1

公开(公告)日：2023-04-27

申请号：US17862586

申请日：2022-07-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junwoo Park ,  Sangsoo Kim ,  Seunghwan Kim ,  Jungjoo Kim ,  Yongkwan Lee

IPC: H01L25/16 ,  H01L23/498 ,  H01L23/64

Abstract: A semiconductor package includes a package substrate including a base substrate including a redistribution layer, pads disposed on first and second surfaces of the base substrate and connected to the redistribution layer, and a protective layer having a mounting region in which first openings respectively exposing first pads among the pads and a second opening exposing second pads among the pads and a portion of the second surface are disposed on the second surface; a semiconductor chip disposed on the mounting region and connected to the pads through the first openings and the second opening; and a sealing material covering a portion of the semiconductor chip and extending into the second opening. Four first openings among the first openings are respectively disposed adjacent to respective corners of the mounting region. The second opening is disposed to divide the four first openings into at least two groups.

公开(公告)号：US20220367416A1

公开(公告)日：2022-11-17

申请号：US17671065

申请日：2022-02-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongkwan Lee ,  Seunghwan Kim ,  Jungjoo Kim ,  Jongwan Kim ,  Hyunki Kim ,  Junwoo Park ,  Hyunggil Baek ,  Junga Lee ,  Taejun Jeon

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538

Abstract: A semiconductor package includes a package substrate having a communication hole extending from an upper surface of the package substrate to a lower surface of the package substrate, a semiconductor chip attached to the upper surface of the package substrate, an auxiliary chip attached to the lower surface of the package substrate, external connection terminals attached to the lower surface of the package substrate and spaced apart from the auxiliary chip, and an encapsulant encapsulating the semiconductor chip and the auxiliary chip and filling the communication hole.

公开(公告)号：US11843947B2

公开(公告)日：2023-12-12

申请号：US17432404

申请日：2020-02-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Donghyun Cho ,  Jinwoo Jang ,  Junwoo Park ,  Youngsok Song ,  Rakyoung Yoon

IPC: H04W12/069 ,  H04W12/71 ,  H04W12/033

CPC classification number: H04W12/069 ,  H04W12/033 ,  H04W12/71

Abstract: An electronic device and an authentication method in the electronic device are provided. The electronic device includes a communication circuit; and at least one processor operatively connected to the communication circuit. The at least one processor may be configured to confirm the occurrence of an authentication event for communication-related security data; in response to the occurrence of the authentication event, confirm at least one piece of communication-related security data stored in a designated area of the electronic device; transmit a certificate request message including the at least one confirmed piece of communication-related security data, to an authentication server by means of the communication circuit; receive a certificate, generated based on at least one communication-related security data included in the transmitted certificate request message from the authentication server through the communication circuit; and authenticate use authority of the communication-related security data, based on the received certificate.

公开(公告)号：US20230082412A1

公开(公告)日：2023-03-16

申请号：US17747131

申请日：2022-05-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongkwan Lee ,  Seunghwan Kim ,  Jungjoo Kim ,  Jongwan Kim ,  Junwoo Park

IPC: H01L23/367 ,  H01L25/065 ,  H01L25/16 ,  H01L23/498 ,  H01L23/48

Abstract: A semiconductor package is provided. The semiconductor package includes a package substrate, an interposer including a lower protective layer, conductive connectors connecting the package substrate to the interposer, a semiconductor chip arranged between the package substrate and the interposer, and cooling patches arranged between the semiconductor chip and the interposer and having cylindrical shapes, wherein each of the cooling patches includes the same material as each of the conductive connectors, a height of each of the cooling patches is less than or equal to a diameter of each of the cooling patches, and thermal conductivity of each of the cooling patches is greater than thermal conductivity of the lower protective layer.

公开(公告)号：US12256465B2

公开(公告)日：2025-03-18

申请号：US17841826

申请日：2022-06-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Donghyun Cho ,  Hanjae Jeong ,  Hyunchool Chung ,  Seungjoo Na ,  Youcheol Moon ,  Junwoo Park ,  Jisun Lee ,  Sangyoung Ju

IPC: H04W88/02 ,  H04W8/18 ,  H04W8/24 ,  H04W12/06 ,  H04W12/71 ,  H04W12/72

Abstract: An electronic device according to an embodiment of the disclosure may include a communication module, a subscriber identification module, and at least one processor. The at least one processor may identify identification information of the subscriber identification module stored in the subscriber identification module when the subscriber identification module is identified as being first inserted, may configure a network service provider based on the identified identification information, may generate a signature by using lock information of the subscriber identification module, may identify network lock information when the signature is identified as being valid, and may set up a network lock function of the communication module based on the identified network lock information.

公开(公告)号：US12205925B2

公开(公告)日：2025-01-21

申请号：US17671065

申请日：2022-02-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongkwan Lee ,  Seunghwan Kim ,  Jungjoo Kim ,  Jongwan Kim ,  Hyunki Kim ,  Junwoo Park ,  Hyunggil Baek ,  Junga Lee ,  Taejun Jeon

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538

Abstract: A semiconductor package includes a package substrate having a communication hole extending from an upper surface of the package substrate to a lower surface of the package substrate, a semiconductor chip attached to the upper surface of the package substrate, an auxiliary chip attached to the lower surface of the package substrate, external connection terminals attached to the lower surface of the package substrate and spaced apart from the auxiliary chip, and an encapsulant encapsulating the semiconductor chip and the auxiliary chip and filling the communication hole.

公开(公告)号：US20230378094A1

公开(公告)日：2023-11-23

申请号：US18104650

申请日：2023-02-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junwoo Park ,  Yongkwan Lee ,  Seunghwan Kim ,  Jungjoo Kim ,  Jongwan Kim ,  Taejun Jeon ,  Junhyeung Jo

IPC: H01L23/00 ,  H01L23/538 ,  H01L23/498 ,  H01L23/31 ,  H10B80/00

CPC classification number: H01L23/562 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5385 ,  H01L23/49811 ,  H01L23/3128 ,  H10B80/00 ,  H01L2224/16227 ,  H01L24/16 ,  H01L2224/32225 ,  H01L24/32 ,  H01L2224/73204 ,  H01L24/73

Abstract: A semiconductor package includes a support wiring structure, a semiconductor chip on the support wiring structure, a connection structure on the support wiring structure and spaced apart from the semiconductor chip in a horizontal direction, an interposer including a central portion and an outer portion and having a recess portion provided on a lower surface of the central portion facing the semiconductor chip, wherein the central portion is on the semiconductor chip and the connection structure is connected to the outer portion, and a metal plate disposed along a portion of a surface of the recess portion inside the interposer, wherein the metal plate extends along a side surface of the outer portion of the interposer and the lower surface of the central portion of the interposer, and the metal plate has a cavity passing through a vicinity of a center of the metal plate planarly.

公开(公告)号：US20230260926A1

公开(公告)日：2023-08-17

申请号：US18107143

申请日：2023-02-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongkwan Lee ,  Seunghwan Kim ,  Jungjoo Kim ,  Jongwan Kim ,  Junwoo Park ,  Hyunggil Baek ,  Junga Lee

IPC: H01L23/544 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L25/10 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/544 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/562 ,  H01L25/105 ,  H01L23/5383 ,  H01L23/5385 ,  H01L21/4846 ,  H01L21/563 ,  H01L2224/16227 ,  H01L24/16 ,  H01L2224/32225 ,  H01L24/32 ,  H01L2224/73204 ,  H01L24/73 ,  H01L2223/54426 ,  H01L2224/92125 ,  H01L24/92

Abstract: A semiconductor package includes an interposer including an upper pad and an upper passivation layer partially covering the upper pad, a semiconductor chip disposed on the interposer, a conductor pattern disposed on the interposer, a guide pattern disposed on the interposer while including a main opening and at least one sub-opening connected to the main opening, a support disposed on the interposer while including a core portion and a peripheral portion surrounding the core portion, a lower surface of the support being disposed in the main opening of the guide pattern, an upper redistribution structure disposed on the semiconductor chip and connected to the conductor pattern and the guide pattern, and an encapsulant between the interposer and the upper redistribution structure. The encapsulant contacts an inner wall of the main opening, an inner wall of the at least one sub-opening and a side surface of the support.

公开(公告)号：US20230411259A1

公开(公告)日：2023-12-21

申请号：US18110994

申请日：2023-02-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunchul Kim ,  Junwoo Park ,  Hyunggil Baek ,  Yongkwan Lee ,  Juhyung Lee

IPC: H01L23/498 ,  H01L23/31

CPC classification number: H01L23/49811 ,  H01L23/49833 ,  H01L24/16 ,  H01L23/3128 ,  H01L2224/16227 ,  H01L23/49822

Abstract: A semiconductor package includes: a lower substrate; a semiconductor chip disposed on the lower substrate; an upper substrate disposed on the semiconductor chip, having a lower surface facing the semiconductor chip, and including step structures disposed below the lower surface; a connection structure disposed around the semiconductor chip and connecting the lower substrate to the upper substrate; and an encapsulant filling a space between the lower substrate and the upper substrate and sealing at least a portion of each of the semiconductor chip and the connection structure. The lower surface of the upper substrate has a first surface portion on which the step structures are disposed and a second surface portion having a step with respect to the lower surface of the step structures, and the second surface portion extends between opposite edges of the upper substrate.

公开(公告)号：US20240128190A1

公开(公告)日：2024-04-18

申请号：US18486546

申请日：2023-10-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seunghwan Kim ,  Yongkwan Lee ,  Gyuhyeong Kim ,  Jungjoo Kim ,  Jongwan Kim ,  Junwoo Park ,  Taejun Jeon ,  Junhyeung Jo

IPC: H01L23/528 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/5283 ,  H01L21/485 ,  H01L21/56 ,  H01L23/3157 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/05008 ,  H01L2224/13026

Abstract: A semiconductor package includes a lower substrate including a lower interconnection layer; an upper substrate on the lower substrate, a recessed surface having a step difference, and an upper interconnection layer having a through-hole extending from the recessed surface to the first surface of the upper substrate and electrically connected to the lower interconnection layer; semiconductor chip between the recessed surface of the upper substrate and the lower substrate and including connection pads electrically connected to the lower interconnection layer; interconnect structure between the second surface of the upper substrate and the lower substrate and electrically connecting the lower interconnection layer to the upper interconnection layer; and an insulating member including a first portion covering at least a portion of the semiconductor chip and interconnect structure, a second portion extending from the first portion into the through-hole, and a third portion covering at least a portion of the first surface.