An apparatus is provided which comprises: a receiver to receive a differential clock; a delay locked loop (DLL) coupled to the receiver; a first phase interpolator (PI) coupled to the DLL, the first PI to provide a first clock phase; a second PI coupled to the DLL, wherein the second PI is to provide a second or third clock phase; circuitry to adjust the first and second PIs according to the first clock phase, and the second or third clock phase.