- Patent Title: Sense circuit with two-step clock signal for consecutive sensing
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Application No.: US15630079Application Date: 2017-06-22
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Publication No.: US10366729B2Publication Date: 2019-07-30
- Inventor: Tai-Yuan Tseng , Anirudh Amarnath
- Applicant: SanDisk Technologies LLC
- Applicant Address: US TX Addison
- Assignee: SanDisk Technologies LLC
- Current Assignee: SanDisk Technologies LLC
- Current Assignee Address: US TX Addison
- Agency: Vierra Magen Marcus LLP
- Main IPC: G11C11/16
- IPC: G11C11/16 ; G11C7/08 ; G11C7/12 ; G11C16/26 ; G11C16/04 ; G11C16/34 ; G11C13/00 ; G11C11/56 ; G11C16/08 ; G11C16/32

Abstract:
A sense circuit is provided in which the threshold voltage of a memory cell is sensed relative to two different levels using a single control gate voltage on the memory cell. These two levels can be lower and higher verify voltages of a data state in a programming operation, or two read levels of a read operation. A sense node is charged up to a peak level by a pre-charge voltage and by capacitive coupling. The sense node then discharges into the bit line. The sense node voltage is decreased first and second times by capacitive coupling after which first and second bits of data are output based on a level of the sense node. The first and second bits indicate a level of the sense node relative to the lower and higher verify voltages, respectively.
Public/Granted literature
- US20180374518A1 Sense Circuit With Two-Step Clock Signal For Consecutive Sensing Public/Granted day:2018-12-27
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