Invention Grant
- Patent Title: Sequential integration process
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Application No.: US15701743Application Date: 2017-09-12
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Publication No.: US10367031B2Publication Date: 2019-07-30
- Inventor: Amey Mahadev Walke , Anne Vandooren , Nadine Collaert
- Applicant: IMEC VZW
- Applicant Address: BE Leuven
- Assignee: IMEC VZW
- Current Assignee: IMEC VZW
- Current Assignee Address: BE Leuven
- Agency: McDonnell Boehnen Hulbert & Berghoff LLP
- Priority: EP16188504 20160913
- Main IPC: H01L23/40
- IPC: H01L23/40 ; H01L27/148 ; H01L21/768 ; H01L21/822 ; H01L27/06 ; H01L29/417 ; H01L31/0216 ; H01L21/8258 ; B28D1/00 ; H01L21/304 ; H01L31/0224

Abstract:
A sequential integration process is described. An example process involves forming a wafer stack by bonding a first wafer to a second wafer with a front side of the first wafer facing a front side of the second wafer, the first wafer including a first device region formed on the front side of the first wafer and including a set of semiconductor devices. The example process involves, subsequent to forming the wafer stack, forming a second device region on a back side of the first wafer, the second device region including a set of semiconductor devices. The example process involves forming at least one interconnection layer on the second device region for electrically interconnecting the semiconductor devices of the second device region. The example process also involves forming at least one via extending through the wafer stack from the at least one interconnection layer and through the first wafer.
Public/Granted literature
- US20180076260A1 Sequential Integration Process Public/Granted day:2018-03-15
Information query
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