Invention Grant
- Patent Title: Selective gate spacers for semiconductor devices
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Application No.: US15506101Application Date: 2014-09-26
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Publication No.: US10396176B2Publication Date: 2019-08-27
- Inventor: Scott B. Clendenning , Szuya S. Liao , Florian Gstrein , Rami Hourani , Patricio E. Romero , Grant M. Kloster , Martin M. Mitan
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Green, Howard & Mughal LLP
- International Application: PCT/US2014/057585 WO 20140926
- International Announcement: WO2016/048336 WO 20160331
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/66 ; H01L21/306 ; H01L21/304 ; H01L29/161 ; H01L29/423 ; H01L29/51 ; H01L29/775 ; H01L29/06 ; H01L21/28 ; H01L29/49 ; H01L21/265 ; H01L21/266

Abstract:
Techniques related to forming selective gate spacers for semiconductor devices and transistor structures and devices formed using such techniques are discussed. Such techniques include forming a blocking material on a semiconductor fin, disposing a gate having a different surface chemistry than the blocking material on a portion of the blocking material, forming a selective conformal layer on the gate but not on a portion of the blocking material, and removing exposed portions of the blocking material.
Public/Granted literature
- US20180219080A1 SELECTIVE GATE SPACERS FOR SEMICONDUCTOR DEVICES Public/Granted day:2018-08-02
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