Invention Grant
- Patent Title: Semiconductor device and method of forming wire studs as vertical interconnect in FO-WLP
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Application No.: US15218847Application Date: 2016-07-25
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Publication No.: US10446523B2Publication Date: 2019-10-15
- Inventor: Pandi C. Marimuthu , Sheila Marie L. Alvarez , Yaojian Lin , Jose A. Caparas , Yang Kern Jonathan Tan
- Applicant: STATS ChipPAC Pte. Ltd.
- Applicant Address: SG Singapore
- Assignee: STATS ChipPAC Pte. Ltd.
- Current Assignee: STATS ChipPAC Pte. Ltd.
- Current Assignee Address: SG Singapore
- Agency: Patent Law Group: Atkins and Associates, P.C.
- Agent Robert D. Atkins
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L25/065 ; H01L23/498 ; H01L21/56 ; H01L23/00 ; H01L23/538 ; H01L25/10 ; H01L21/311 ; H01L21/48 ; H01L23/31 ; H01L21/263

Abstract:
A semiconductor device has a substrate and semiconductor die disposed over a first surface of the substrate. A wire stud is attached to the first surface of the substrate. The wire stud includes a base portion and stem portion. A bonding pad is formed over a second surface of the substrate. An encapsulant is deposited over the substrate, semiconductor die, and wire stud. A portion of the encapsulant is removed by LDA to expose the wire stud. A portion of the encapsulant is removed by LDA to expose the substrate. An interconnect structure is formed over the encapsulant and electrically connected to the wire stud and semiconductor die. A bump is formed over the interconnect structure. A semiconductor package is disposed over the encapsulant and electrically connected to the substrate. A discrete semiconductor device is disposed over the encapsulant and electrically connected to the substrate.
Public/Granted literature
- US20160336299A1 Semiconductor Device and Method of Forming Wire Studs as Vertical Interconnect in FO-WLP Public/Granted day:2016-11-17
Information query
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