Invention Grant
- Patent Title: Structure and formation method of isolation feature of semiconductor device structure
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Application No.: US15663089Application Date: 2017-07-28
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Publication No.: US10658490B2Publication Date: 2020-05-19
- Inventor: Kuo-Cheng Ching , Shi-Ning Ju , Kuan-Ting Pan , Kuan-Lun Cheng , Chih-Hao Wang
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Birch, Stewart, Kolasch & Birch, LLP
- Main IPC: H01L21/8234
- IPC: H01L21/8234 ; H01L29/66 ; H01L21/311 ; H01L21/762 ; H01L21/8238 ; H01L29/06 ; H01L29/08 ; H01L29/16 ; H01L29/161 ; H01L29/78 ; H01L21/308 ; H01L29/51

Abstract:
Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. The semiconductor device structure also includes active gate stacks over the fin structure. The semiconductor device structure further includes a dummy gate stack over the fin structure. The dummy gate stack is between the active gate stacks. In addition, the semiconductor device structure includes spacer elements over sidewalls of the dummy gate stack and the active gate stacks. The semiconductor device structure also includes an isolation feature below the dummy gate stack, the active gate stacks and the spacer elements. The isolation feature extends into the fin structure from the bottom of the dummy gate stack such that the isolation feature is surrounded by the fin structure.
Public/Granted literature
- US20190035912A1 STRUCTURE AND FORMATION METHOD OF ISOLATION FEATURE OF SEMICONDUCTOR DEVICE STRUCTURE Public/Granted day:2019-01-31
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