公开(公告)号：US11855079B2

公开(公告)日：2023-12-26

申请号：US17484956

申请日：2021-09-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Chiang ,  Jung-Chien Cheng ,  Shi-Ning Ju ,  Guan-Lin Chen ,  Chih-Hao Wang

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/423 ,  H01L21/762

CPC classification number: H01L27/088 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/4232 ,  H01L29/66477

Abstract: An integrated circuit includes a first nanosheet transistor and a second nanosheet transistor on a substrate. The first and second nanosheet each include gate electrodes. A gate isolation structure extends from a backside of the substrate between the gate electrodes. The gate isolation structure physically and electrically isolates the first and second gate electrodes from each other.

公开(公告)号：US11195936B2

公开(公告)日：2021-12-07

申请号：US16881685

申请日：2020-05-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng Ching ,  Shi-Ning Ju ,  Chih-Hao Wang ,  Ying-Keung Leung

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/311 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/02 ,  H01L29/51

Abstract: A semiconductor structure includes a substrate, a fin, a bottom capping structure and a top capping structure. The fin disposed on the substrate, the fin has a lower portion and an upper portion extending upwards from the lower portion. The bottom capping structure covers a sidewall of the lower portion of the fin. The top capping structure covers a sidewall of the upper portion of the fin.

公开(公告)号：US10886269B2

公开(公告)日：2021-01-05

申请号：US16133795

申请日：2018-09-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng Ching ,  Kuan-Ting Pan ,  Shi-Ning Ju ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L21/00 ,  H01L27/088 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/308

Abstract: A semiconductor device has a substrate, a first dielectric fin, and an isolation structure. The substrate has a first semiconductor fin. The first dielectric fin is disposed over the substrate and in contact with a first sidewall of the first semiconductor fin, in which a width of the first semiconductor fin is substantially equal to a width of the first dielectric fin. The isolation structure is in contact with the first semiconductor fin and the first dielectric fin, in which a top surface of the isolation structure is in a position lower than a top surface of the first semiconductor fin and a top surface of the first dielectric fin.

公开(公告)号：US10700183B2

公开(公告)日：2020-06-30

申请号：US16226827

申请日：2018-12-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng Ching ,  Kuan-Ting Pan ,  Shi-Ning Ju ,  Chih-Hao Wang

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L21/762

Abstract: A method for forming a FinFET device structure includes forming a first fin structure in a core region of a substrate and a second fin structure in an input/output region of the substrate with a fin top layer and a hard mask layer over the fin structures. The method also includes forming a dummy oxide layer across the fin structures. The method also includes forming a dummy gate structure over the dummy oxide layer. The method also includes removing the dummy gate structure over fin structures. The method also includes removing the dummy oxide layer and trimming the fin structures. The method also includes forming first and second oxide layers across the first and second fin structures. The method also includes forming first and second gate structures over the first and second oxide layers across the first and second fin structures.

公开(公告)号：US20190081153A1

公开(公告)日：2019-03-14

申请号：US16186783

申请日：2018-11-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng Ching ,  Shi-Ning Ju ,  Chih-Hao Wang ,  Ying-Keung Leung

IPC: H01L29/66 ,  H01L21/311 ,  H01L21/02 ,  H01L29/51 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/78

CPC classification number: H01L29/6653 ,  H01L21/0214 ,  H01L21/02247 ,  H01L21/02271 ,  H01L21/31116 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/513 ,  H01L29/518 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor structure includes a substrate, a fin, a bottom capping structure and a top capping structure. The fin disposed on the substrate, the fin has a lower portion and an upper portion extending upwards from the lower portion. The bottom capping structure covers a sidewall of the lower portion of the fin. The top capping structure covers a sidewall of the upper portion of the fin.

公开(公告)号：US10134870B2

公开(公告)日：2018-11-20

申请号：US15409617

申请日：2017-01-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng Ching ,  Shi-Ning Ju ,  Chih-Hao Wang ,  Ying-Keung Leung

IPC: H01L21/82 ,  H01L29/66 ,  H01L21/02 ,  H01L29/51 ,  H01L21/311

Abstract: A semiconductor structure includes a substrate, a fin, a bottom capping structure and a top capping structure. The fin disposed on the substrate, the fin has a lower portion and an upper portion extending upwards from the lower portion. The bottom capping structure covers a sidewall of the lower portion of the fin. The top capping structure covers a sidewall of the upper portion of the fin.

公开(公告)号：US12107153B2

公开(公告)日：2024-10-01

申请号：US18298073

申请日：2023-04-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng Ching ,  Shi-Ning Ju ,  Kuan-Ting Pan ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H10B10/00

CPC classification number: H01L29/6681 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0653 ,  H10B10/12

Abstract: A first semiconductor fin is over the first region of the substrate and extends along a first direction. A second semiconductor fin is over the second region of the substrate and extends along the first direction. A dielectric structure is over the first region of the substrate and is in contact with a longitudinal end of the first semiconductor fin, wherein the dielectric structure is wider than the first semiconductor fin along a second direction perpendicular to the first direction. A first dielectric fin is over the second region of the substrate and is in contact with a longitudinal end of the second semiconductor fin, wherein the first dielectric fin and the second semiconductor fin have substantially a same width along the second direction.

公开(公告)号：US12062705B2

公开(公告)日：2024-08-13

申请号：US17106933

申请日：2020-11-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Hao Wang ,  Shi-Ning Ju ,  Kai-Chieh Yang ,  Wen-Ting Lan ,  Wai-Yi Lien

IPC: H01L29/423 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/42392 ,  H01L21/31053 ,  H01L21/31144 ,  H01L21/823487 ,  H01L21/823885 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/0649

Abstract: According to an exemplary embodiment, a method of forming a vertical structure is provided. The method includes the following operations: providing a substrate; providing the vertical structure having a source, a channel, and a drain over the substrate; shrinking the source and the channel by oxidation; forming a metal layer over the drain of the vertical structure; and annealing the metal layer to form a silicide over the drain of the vertical structure.

公开(公告)号：US11362001B2

公开(公告)日：2022-06-14

申请号：US16911665

申请日：2020-06-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsiao-Han Liu ,  Chih-Hao Wang ,  Kuo-Cheng Chiang ,  Shi-Ning Ju ,  Kuan-Lun Cheng

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/78

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a first fin structure, a second fin structure, a third fin structure, and a fourth fin structure formed over a substrate. The semiconductor structure further includes first nanostructures, second nanostructures, third nanostructures, and fourth nanostructures. The semiconductor structure further includes a first gate structure wrapping around the first nanostructures and the second nanostructures, and a second gate structure wrapping around the third nanostructures and the fourth nanostructures. In addition, a first lateral distance between the first fin structure and the second fin structure is shorter than a second lateral distance between the third fin structure and the fourth fin structure, and the first fin structure and the second fin structure are narrower than the third fin structure and the fourth fin structure.

公开(公告)号：US11302693B2

公开(公告)日：2022-04-12

申请号：US17007742

申请日：2020-08-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jia-Chuan You ,  Shi-Ning Ju ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC: H01L29/76 ,  H01L29/94 ,  H01L27/088 ,  H01L23/528 ,  H01L21/8234 ,  H01L21/768

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first, second, and third gate electrode layers, a first dielectric feature disposed between the first and second gate electrode layers, a second dielectric feature disposed between the second and third gate electrode layers, a first seed layer in contact with the first gate electrode layer, the first dielectric feature, and the second gate electrode layer, a first conductive layer disposed on the first seed layer, a second seed layer in contact with the third gate electrode layer, a second conductive layer disposed on the second seed layer, and a dielectric material disposed on the second dielectric feature, the first conductive layer, and the second conductive layer. The dielectric material is between the first seed layer and the second seed layer and between the first conductive layer and the second conductive layer.