Invention Grant
- Patent Title: Quantum circuit assemblies with at least partially buried transmission lines and capacitors
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Application No.: US16012815Application Date: 2018-06-20
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Publication No.: US10686007B2Publication Date: 2020-06-16
- Inventor: Hubert C. George , Adel A. Elsherbini , Lester Lampert , James S. Clarke , Ravi Pillarisetty , Zachary R. Yoscovits , Nicole K. Thomas , Roman Caudillo , Kanwaljit Singh , David J. Michalak , Jeanette M. Roberts
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Patent Capital Group
- Main IPC: H01L27/18
- IPC: H01L27/18 ; H01L39/22 ; H01L49/02 ; G06N10/00 ; H01L39/02 ; H01L39/24 ; H03K19/195

Abstract:
Embodiments of the present disclosure propose quantum circuit assemblies with transmission lines and/or capacitors that include layer-conductors oriented perpendicular to a substrate (i.e. oriented vertically) or a qubit die, with at least portions of the vertical layer-conductors being at least partially buried in the substrate. Such layer-conductors may form ground and signal planes of transmission lines or capacitor plates of capacitors of various quantum circuit assemblies.
Public/Granted literature
- US20190043919A1 QUANTUM CIRCUIT ASSEMBLIES WITH AT LEAST PARTIALLY BURIED TRANSMISSION LINES AND CAPACITORS Public/Granted day:2019-02-07
Information query
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