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公开(公告)号：US11450765B2
公开(公告)日：2022-09-20
申请号：US16143676
申请日：2018-09-27
申请人： Intel Corporation
发明人： Hubert C. George , Ravi Pillarisetty , Lester Lampert , James S. Clarke , Nicole K. Thomas , Roman Caudillo , Kanwaljit Singh , David J. Michalak , Jeanette M. Roberts
IPC分类号： H01L29/778 , H01L29/51 , H01L29/49 , H01L29/15 , H01L27/02 , H01L29/82 , H01L29/66 , H01L23/538 , G06N10/00
摘要： A quantum dot device is disclosed that includes a fin and a gate above the fin. The fin may extend away from a base and include a quantum well stack in which one or more quantum dots may be formed during operation of the quantum dot device. The gate may include a gate electrode material having a first portion and a second portion, where the first portion is above the quantum well stack and the second portion is a portion that is not above the quantum well stack and is separated from the base by an insulating material. The quantum dot device may further include a metal structure between the second portion of the gate electrode material and the base, forming a portion of a diode provided in series with the gate, which diode may provide at least some ESD protection for the quantum dot device.
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公开(公告)号：US11183564B2
公开(公告)日：2021-11-23
申请号：US16015087
申请日：2018-06-21
申请人： Intel Corporation
发明人： Nicole K. Thomas , Ravi Pillarisetty , Payam Amin , Roza Kotlyar , Patrick H. Keys , Hubert C. George , Kanwaljit Singh , James S. Clarke , David J. Michalak , Lester Lampert , Zachary R. Yoscovits , Roman Caudillo , Jeanette M. Roberts
IPC分类号： H01L29/12 , H01L29/66 , H01L29/76 , H01L29/423 , H01L29/165 , H01L27/18 , H01L21/8234 , H01L29/10 , G06N10/00 , H01L39/14 , H01L29/06 , B82Y10/00 , H01L29/82 , H01L29/40 , H01L21/321 , H01L21/02 , H01L29/778 , H01L29/43
摘要： Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer and a barrier layer; a first gate metal above the quantum well stack, wherein the barrier layer is between the first gate metal and the quantum well layer; and a second gate metal above the quantum well stack, wherein the barrier layer is between the second gate metal and the quantum well layer, and a material structure of the second gate metal is different from a material structure of the first gate metal.
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公开(公告)号：US20210296473A1
公开(公告)日：2021-09-23
申请号：US17342093
申请日：2021-06-08
摘要： Quantum dot devices, and related systems and methods, are disclosed herein. In some embodiments, a quantum dot device may include a quantum well stack having a first face and a second opposing face; an array of parallel first gate lines at the first face or the second face of the quantum well stack; and an array of parallel second gate lines at the first face or the second face of the quantum well stack, wherein the second gate lines are oriented diagonal to the first gate lines.
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公开(公告)号：US20200373351A1
公开(公告)日：2020-11-26
申请号：US16635193
申请日：2017-09-18
申请人： Intel Corporation
发明人： Jeanette M. Roberts , Wesley T. Harrison , Adel A. Elsherbini , Stefano Pellerano , Zachary R. Yoscovits , Lester Lampert , Ravi Pillarisetty , Roman Caudillo , Hubert C. George , Nicole K. Thomas , David J. Michalak , Kanwaljit Singh , James S. Clarke
摘要： Embodiments of the present disclosure propose qubit substrates, as well as methods of fabricating thereof and related device assemblies. In one aspect of the present disclosure, a qubit substrate includes a base substrate of a doped semiconductor material, and a layer of a substantially intrinsic semiconductor material over the base substrate. Engineering a qubit substrate in this manner allows improving coherence times of qubits provided thereon, while, at the same time, being sufficiently mechanically robust so that it can be efficiently used in large-scale manufacturing.
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公开(公告)号：US20200312989A1
公开(公告)日：2020-10-01
申请号：US16365018
申请日：2019-03-26
申请人： Intel Corporation
发明人： Hubert C. George , Sarah Atanasov , Ravi Pillarisetty , Lester Lampert , James S. Clarke , Nicole K. Thomas , Roman Caudillo , Kanwaljit Singh , David J. Michalak , Jeanette M. Roberts , Stephanie A. Bojarski
IPC分类号： H01L29/775 , H01L29/423 , H01L29/78 , H01L29/66 , G06N10/00
摘要： Disclosed herein are quantum dot devices with multiple layers of gate metal, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; an insulating material above the quantum well stack, wherein the insulating material includes a trench; and a gate on the insulating material and extending into the trench, wherein the gate includes a first gate metal in the trench and a second gate metal above the first gate metal.
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公开(公告)号：US20190334020A1
公开(公告)日：2019-10-31
申请号：US16349955
申请日：2016-12-14
申请人： Intel Corporation
发明人： Payam Amin , Nicole K. Thomas , James S. Clarke , Jessica M. Torres , Ravi Pillarisetty , Hubert C. George , Kanwaljit Singh , Van H. Le , Jeanette M. Roberts , Roman Caudillo , Zachary R. Yoscovits , David J. Michalak
IPC分类号： H01L29/775 , H01L29/12 , H01L29/165 , H01L29/66 , H01L21/02 , G06N10/00
摘要： Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum processing device may include: a quantum well stack having alternatingly arranged relaxed and strained layers; and a plurality of gates disposed above the quantum well stack to control quantum dot formation in the quantum well stack.
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公开(公告)号：US20190044045A1
公开(公告)日：2019-02-07
申请号：US15924410
申请日：2018-03-19
申请人： Intel Corporation
发明人： Nicole K. Thomas , James S. Clarke , Jessica M. Torres , Lester Lampert , Ravi Pillarisetty , Hubert C. George , Kanwaljit Singh , Jeanette M. Roberts , Roman Caudillo , Zachary R. Yoscovits , David J. Michalak
CPC分类号： H01L39/025 , B82Y10/00 , G06N10/00 , H01L29/127 , H01L29/423 , H01L29/66439 , H01L29/66977 , H01L29/66984 , H01L29/7613 , H01L39/045 , H01L39/223 , H01L39/249 , H01L39/2493 , H03K17/92
摘要： Embodiments of the present disclosure describe use of isotopically purified materials in donor- or acceptor-based spin qubit devices and assemblies. An exemplary spin qubit device assembly may include a semiconductor host layer that includes an isotopically purified material, a dopant atom in the semiconductor host layer, and a gate proximate to the dopant atom. An isotopically purified material may include a lower atomic-percent of isotopes with nonzero nuclear spin than the natural abundance of those isotopies in the non-isotopically purified material. Reducing the presence of isotopes with nonzero nuclear spin in a semiconductor host layer may improve qubit coherence and thus performance of spin qubit devices and assemblies.
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公开(公告)号：US20190043975A1
公开(公告)日：2019-02-07
申请号：US16017031
申请日：2018-06-25
申请人： Intel Corporation
发明人： Hubert C. George , David J. Michalak , Ravi Pillarisetty , Lester Lampert , James S. Clarke , Zachary R. Yoscovits , Nicole K. Thomas , Roman Caudillo , Kanwaljit Singh , Jeanette M. Roberts
IPC分类号： H01L29/778 , H01L29/12 , H01L29/06 , H01L29/66 , H01L21/8234 , H01L29/15 , H01L27/088 , H01L29/10 , G06N99/00
摘要： Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a base; a fin extending away from the base, wherein the fin includes a quantum well layer; a first dielectric material around a bottom portion of the fin; and a second dielectric material around a top portion of the fin, wherein the second dielectric material is different from the first dielectric material.
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公开(公告)号：US20190043968A1
公开(公告)日：2019-02-07
申请号：US15924407
申请日：2018-03-19
申请人： Intel Corporation
发明人： Lester Lampert , James S. Clarke , Jeanette M. Roberts , Ravi Pillarisetty , David J. Michalak , Kanwaljit Singh , Roman Caudillo , Hubert C. George , Zachary R. Yoscovits , Nicole K. Thomas
摘要： Embodiments of the present disclosure describe a method of fabricating spin qubit device assemblies that utilize dopant-based spin qubits, i.e. spin qubit devices which operate by including a donor or an acceptor dopant atom in a semiconductor host layer. The method includes, first, providing a pair of gate electrodes over a semiconductor host layer, and then providing a window structure between the first and second gate electrodes, the window structure being a continuous solid material extending between the first and second electrodes and covering the semiconductor host layer except for an opening through which a dopant atom is to be implanted in the semiconductor host layer. By using a defined gate-first process, the method may address the scalability challenges and create a deterministic path for fabricating dopant-based spin qubits in desired locations, promoting wafer-scale integration of dopant-based spin qubit devices for use in quantum computing devices.
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公开(公告)号：US20190043951A1
公开(公告)日：2019-02-07
申请号：US16015087
申请日：2018-06-21
申请人： Intel Corporation
发明人： Nicole K. Thomas , Ravi Pillarisetty , Payam Amin , Roza Kotlyar , Patrick H. Keys , Hubert C. George , Kanwaljit Singh , James S. Clarke , David J. Michalak , Lester Lampert , Zachary R. Yoscovits , Roman Caudillo , Jeanette M. Roberts
IPC分类号： H01L29/12 , H01L29/10 , H01L29/423 , H01L29/165 , H01L21/02 , H01L29/66 , H01L29/778 , G06N99/00
摘要： Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer and a barrier layer; a first gate metal above the quantum well stack, wherein the barrier layer is between the first gate metal and the quantum well layer; and a second gate metal above the quantum well stack, wherein the barrier layer is between the second gate metal and the quantum well layer, and a material structure of the second gate metal is different from a material structure of the first gate metal.
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