Invention Grant
- Patent Title: Scan synchronous-write-through testing architectures for a memory device
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Application No.: US15700877Application Date: 2017-09-11
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Publication No.: US10705934B2Publication Date: 2020-07-07
- Inventor: Ming-Hung Chang , Atul Katoch , Chia-En Huang , Ching-Wei Wu , Donald G. Mikan, Jr. , Hao-I Yang , Kao-Cheng Lin , Ming-Chien Tsai , Saman M. I. Adham , Tsung-Yung Chang , Uppu Sharath Chandra
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW
- Agency: Sterne, Kessler, Goldstein & Fox P.L.L.C.
- Main IPC: G06F11/263
- IPC: G06F11/263 ; G06F1/10 ; G06F11/22 ; G06F11/267 ; G11C29/48 ; G11C29/32 ; G11C29/12

Abstract:
An exemplary testing environment can operate in a testing mode of operation to test whether a memory device or other electronic devices communicatively coupled to the memory device operate as expected or unexpectedly as a result of one or more manufacturing faults. The testing mode of operation includes a shift mode of operation, a capture mode of operation, and/or a scan mode of operation. In the shift mode of operation and the scan mode of operation, the exemplary testing environment delivers a serial input sequence of data to the memory device. In the capture mode of operation, the exemplary testing environment delivers a parallel input sequence of data to the memory device. The memory device thereafter passes through the serial input sequence of data or the parallel input sequence of data to provide an output sequence of data in the shift mode of operation or the capture mode of operation or passes through the serial input sequence of data to provide a serial output sequence of scan data in the scan mode of operation.
Public/Granted literature
- US20190004915A1 SCAN SYNCHRONOUS-WRITE-THROUGH TESTING ARCHITECTURES FOR A MEMORY DEVICE Public/Granted day:2019-01-03
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