公开(公告)号：US11734142B2

公开(公告)日：2023-08-22

申请号：US17651595

申请日：2022-02-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Hung Chang ,  Atul Katoch ,  Chia-En Huang ,  Ching-Wei Wu ,  Donald G. Mikan, Jr. ,  Hao-I Yang ,  Kao-Cheng Lin ,  Ming-Chien Tsai ,  Saman M. I. Adham ,  Tsung-Yung Chang ,  Uppu Sharath Chandra

IPC: G06F11/263 ,  G06F1/10 ,  G06F11/22 ,  G06F11/267 ,  G11C29/12 ,  G11C29/32 ,  G11C29/48

CPC classification number: G06F11/263 ,  G06F1/10 ,  G06F11/2273 ,  G06F11/267 ,  G11C29/1201 ,  G11C29/32 ,  G11C29/48

Abstract: An exemplary testing environment can operate in a testing mode of operation to test whether a memory device or other electronic devices communicatively coupled to the memory device operate as expected or unexpectedly as a result of one or more manufacturing faults. The testing mode of operation includes a shift mode of operation, a capture mode of operation, and/or a scan mode of operation. In the shift mode of operation and the scan mode of operation, the exemplary testing environment delivers a serial input sequence of data to the memory device. In the capture mode of operation, the exemplary testing environment delivers a parallel input sequence of data to the memory device. The memory device thereafter passes through the serial input sequence of data or the parallel input sequence of data to provide an output sequence of data in the shift mode of operation or the capture mode of operation or passes through the serial input sequence of data to provide a serial output sequence of scan data in the scan mode of operation.

公开(公告)号：US10522202B2

公开(公告)日：2019-12-31

申请号：US15960406

申请日：2018-04-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Sanjeev Kumar Jain ,  Atul Katoch

IPC: G11C7/22 ,  G11C7/12 ,  G11C7/06 ,  H03K5/134 ,  H03K5/135 ,  H03K5/00

Abstract: A circuit is disclosed that includes an inverter unit and a switch unit. The inverter unit is coupled to a memory cell column. The inverter unit is configured to invert, in response to a first control signal and a second control signal, a first signal and to output a second signal for the enabling or disabling of a bit line keeper circuit that is configured to maintain a bit line to a voltage. The first signal is generated by the memory cell column. The switch unit is configured to couple a reference voltage to an input of the inverter unit, in response to a third control signal. The inverter unit is further configured to be deactivated in response to the reference voltage, the first control signal, and the second control signal.

公开(公告)号：US11256588B2

公开(公告)日：2022-02-22

申请号：US16888013

申请日：2020-05-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Hung Chang ,  Atul Katoch ,  Chia-En Huang ,  Ching-Wei Wu ,  Donald G. Mikan, Jr. ,  Hao-I Yang ,  Kao-Cheng Lin ,  Ming-Chien Tsai ,  Saman M. I. Adham ,  Tsung-Yung Chang ,  Uppu Sharath Chandra

IPC: G06F11/263 ,  G06F1/10 ,  G06F11/22 ,  G06F11/267 ,  G11C29/48 ,  G11C29/32 ,  G11C29/12

Abstract: An exemplary testing environment can operate in a testing mode of operation to test whether a memory device or other electronic devices communicatively coupled to the memory device operate as expected or unexpectedly as a result of one or more manufacturing faults. The testing mode of operation includes a shift mode of operation, a capture mode of operation, and/or a scan mode of operation. In the shift mode of operation and the scan mode of operation, the exemplary testing environment delivers a serial input sequence of data to the memory device. In the capture mode of operation, the exemplary testing environment delivers a parallel input sequence of data to the memory device. The memory device thereafter passes through the serial input sequence of data or the parallel input sequence of data to provide an output sequence of data in the shift mode of operation or the capture mode of operation or passes through the serial input sequence of data to provide a serial output sequence of scan data in the scan mode of operation.

公开(公告)号：US09984765B2

公开(公告)日：2018-05-29

申请号：US15621118

申请日：2017-06-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Atul Katoch

IPC: G11C17/00 ,  G11C29/02 ,  G11C29/00 ,  G11C11/417 ,  G11C17/18 ,  G11C17/16

CPC classification number: G11C29/027 ,  G11C11/417 ,  G11C11/419 ,  G11C17/16 ,  G11C17/18 ,  G11C29/12 ,  G11C29/28 ,  G11C29/78

Abstract: A method includes: examining, by a test engine, whether a first bit of a memory array is functional; in response to the first bit being not functional, storing, by the test engine, address information of the first bit into a memory device; and retrieving, by an assist circuit trimming (ACT) circuit, the address information of the first bit from the memory device to selectively activate at least a first one of a plurality of assist circuits associated with the first bit.

公开(公告)号：US10705934B2

公开(公告)日：2020-07-07

申请号：US15700877

申请日：2017-09-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Hung Chang ,  Atul Katoch ,  Chia-En Huang ,  Ching-Wei Wu ,  Donald G. Mikan, Jr. ,  Hao-I Yang ,  Kao-Cheng Lin ,  Ming-Chien Tsai ,  Saman M. I. Adham ,  Tsung-Yung Chang ,  Uppu Sharath Chandra

IPC: G06F11/263 ,  G06F1/10 ,  G06F11/22 ,  G06F11/267 ,  G11C29/48 ,  G11C29/32 ,  G11C29/12

Abstract: An exemplary testing environment can operate in a testing mode of operation to test whether a memory device or other electronic devices communicatively coupled to the memory device operate as expected or unexpectedly as a result of one or more manufacturing faults. The testing mode of operation includes a shift mode of operation, a capture mode of operation, and/or a scan mode of operation. In the shift mode of operation and the scan mode of operation, the exemplary testing environment delivers a serial input sequence of data to the memory device. In the capture mode of operation, the exemplary testing environment delivers a parallel input sequence of data to the memory device. The memory device thereafter passes through the serial input sequence of data or the parallel input sequence of data to provide an output sequence of data in the shift mode of operation or the capture mode of operation or passes through the serial input sequence of data to provide a serial output sequence of scan data in the scan mode of operation.

公开(公告)号：US09824780B2

公开(公告)日：2017-11-21

申请号：US15076416

申请日：2016-03-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Atul Katoch

IPC: G11C29/00 ,  G11C29/44

CPC classification number: G11C29/781 ,  G11C2029/4402

Abstract: A device includes input/output (IO) circuits, a redundant IO circuit and a redundant IO control unit. The input/output (IO) circuits coupled to a memory array. The redundant IO circuit is coupled to the memory array and the plurality of IO circuits. The redundant IO control unit is coupled to the IO circuits and the redundant IO circuit. In response to a failure column address signal, the redundant IO control unit configures the redundant IO circuit to substitute a failed IO circuit of the IO circuits. The redundant IO control unit includes a storage circuit, and during a shutdown mode, the storage circuit is configured to store the failure column address signal.

公开(公告)号：US09704599B1

公开(公告)日：2017-07-11

申请号：US15291761

申请日：2016-10-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Atul Katoch

IPC: G11C17/00 ,  G11C29/02 ,  G11C17/18 ,  G11C17/16 ,  G11C11/417 ,  G11C29/00

CPC classification number: G11C29/027 ,  G11C11/417 ,  G11C11/419 ,  G11C17/16 ,  G11C17/18 ,  G11C29/12 ,  G11C29/28 ,  G11C29/78

Abstract: A memory device includes: a memory array comprising a plurality of bits, wherein a first bit of the plurality of bits is coupled to a first assist circuit; a test engine, coupled to the memory array, and configured to examine whether each bit is functional; and an assist circuit trimming (ACT) circuit, coupled to the memory array and the test engine, and in response to the examination, configured to selectively activate the first assist circuit.