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公开(公告)号：US11734142B2
公开(公告)日：2023-08-22
申请号：US17651595
申请日：2022-02-18
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Ming-Hung Chang , Atul Katoch , Chia-En Huang , Ching-Wei Wu , Donald G. Mikan, Jr. , Hao-I Yang , Kao-Cheng Lin , Ming-Chien Tsai , Saman M. I. Adham , Tsung-Yung Chang , Uppu Sharath Chandra
IPC: G06F11/263 , G06F1/10 , G06F11/22 , G06F11/267 , G11C29/12 , G11C29/32 , G11C29/48
CPC classification number: G06F11/263 , G06F1/10 , G06F11/2273 , G06F11/267 , G11C29/1201 , G11C29/32 , G11C29/48
Abstract: An exemplary testing environment can operate in a testing mode of operation to test whether a memory device or other electronic devices communicatively coupled to the memory device operate as expected or unexpectedly as a result of one or more manufacturing faults. The testing mode of operation includes a shift mode of operation, a capture mode of operation, and/or a scan mode of operation. In the shift mode of operation and the scan mode of operation, the exemplary testing environment delivers a serial input sequence of data to the memory device. In the capture mode of operation, the exemplary testing environment delivers a parallel input sequence of data to the memory device. The memory device thereafter passes through the serial input sequence of data or the parallel input sequence of data to provide an output sequence of data in the shift mode of operation or the capture mode of operation or passes through the serial input sequence of data to provide a serial output sequence of scan data in the scan mode of operation.
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公开(公告)号：US09466493B2
公开(公告)日：2016-10-11
申请号：US13939201
申请日：2013-07-11
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yen-Huei Chen , Chien Chi Tien , Kao-Cheng Lin , Jung-Hsuan Chen
IPC: G01R19/00 , H01L21/28 , G11C7/06 , H01L21/20 , H01L27/092
CPC classification number: G11C7/065 , G11C11/419 , H01L21/20 , H01L21/2003 , H01L21/28008 , H01L21/823431 , H01L21/823475 , H01L23/528 , H01L23/552 , H01L27/0207 , H01L27/0296 , H01L27/0886 , H01L27/0924 , H01L27/1104 , H01L29/0649
Abstract: A sense amplifier (SA) comprises a semiconductor substrate having an oxide definition (OD) region, a pair of SA sensing devices, a SA enabling device, and a sense amplifier enabling signal (SAE) line for carrying an SAE signal. The pair of SA sensing devices have the same poly gate length Lg as the SA enabling device, and they all share the same OD region. When enabled, the SAE signal turns on the SA enabling device to discharge one of the pair of SA sensing devices for data read from the sense amplifier.
Abstract translation: 读出放大器（SA）包括具有氧化物定义（OD）区域的半导体衬底，一对SA感测装置，SA使能装置和用于承载SAE信号的读出放大器使能信号（SAE）线。 一对SA感测装置具有与SA使能装置相同的多栅极长度Lg，并且它们都共享相同的OD区域。 当使能时，SAE信号使SA使能装置打开一对SA感测装置中的一个，以从读出放大器读取数据。
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公开(公告)号：US11264088B2
公开(公告)日：2022-03-01
申请号：US16997857
申请日：2020-08-19
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Wei-Cheng Wu , Chih-Yu Lin , Kao-Cheng Lin , Wei-Min Chan , Yen-Huei Chen
IPC: G11C11/419 , G11C11/413 , H01L27/11 , G11C11/412
Abstract: A device is disclosed that includes a plurality of first memory cells, a plurality of second memory cells, a power circuit, and a header circuit. The power circuit is configured to provide a first power voltage via a conductive line for the plurality of first memory cells, and to provide a second power voltage, that is independent from the first power voltage, for the plurality of second memory cells. The header circuit is configured to provide, during the write operation, the first voltage smaller than the first power voltage, the second power voltage, or smaller than the first power voltage and the second power voltage, for corresponding memory cells of the plurality of first memory cells via the conductive line and for corresponding memory cells of the plurality of second memory cells. A circuit structure of the power circuit is different from a circuit structure of the header circuit.
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公开(公告)号：US11256588B2
公开(公告)日：2022-02-22
申请号：US16888013
申请日：2020-05-29
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Ming-Hung Chang , Atul Katoch , Chia-En Huang , Ching-Wei Wu , Donald G. Mikan, Jr. , Hao-I Yang , Kao-Cheng Lin , Ming-Chien Tsai , Saman M. I. Adham , Tsung-Yung Chang , Uppu Sharath Chandra
IPC: G06F11/263 , G06F1/10 , G06F11/22 , G06F11/267 , G11C29/48 , G11C29/32 , G11C29/12
Abstract: An exemplary testing environment can operate in a testing mode of operation to test whether a memory device or other electronic devices communicatively coupled to the memory device operate as expected or unexpectedly as a result of one or more manufacturing faults. The testing mode of operation includes a shift mode of operation, a capture mode of operation, and/or a scan mode of operation. In the shift mode of operation and the scan mode of operation, the exemplary testing environment delivers a serial input sequence of data to the memory device. In the capture mode of operation, the exemplary testing environment delivers a parallel input sequence of data to the memory device. The memory device thereafter passes through the serial input sequence of data or the parallel input sequence of data to provide an output sequence of data in the shift mode of operation or the capture mode of operation or passes through the serial input sequence of data to provide a serial output sequence of scan data in the scan mode of operation.
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公开(公告)号：US10651114B2
公开(公告)日：2020-05-12
申请号：US16224159
申请日：2018-12-18
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chih-Yu Lin , Kao-Cheng Lin , Li-Wen Wang , Yen-Huei Chen
Abstract: An apparatus and method of three dimensional conductive lines comprising a first memory column segment in a first tier, a second memory column segment in a second tier, and conductive lines connecting the first memory column segment to the second memory column segment. In some embodiments a conductive line is disposed in the first tier on a first side of the memory column and in the second tier on a second side of the memory column.
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Patent Agency Ranking
公开(公告)号：US09997235B2
公开(公告)日：2018-06-12
申请号：US15336633
申请日：2016-10-27
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Wei-Cheng Wu , Chih-Yu Lin , Kao-Cheng Lin , Wei-Min Chan , Yen-Huei Chen
IPC: G11C5/14 , G11C7/00 , G11C11/419
CPC classification number: G11C11/419
Abstract: A device is disclosed that includes first memory cells, second memory cells, a first conductive line and a second conductive line. The first conductive line is electrically disconnected from the second conductive line. The first conductive line receives a first power voltage for the plurality of first memory cells. The second conductive line receives a second power voltage that is independent from the first power voltage, for the plurality of second memory cells.
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公开(公告)号：US11238905B2
公开(公告)日：2022-02-01
申请号：US16830935
申请日：2020-03-26
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yen-Huei Chen , Chien Chi Linus Tien , Kao-Cheng Lin , Jung-Hsuan Chen
IPC: G11C7/06 , H01L21/28 , G11C11/419 , H01L21/8234 , H01L23/528 , H01L23/552 , H01L27/02 , H01L27/088 , H01L27/11 , H01L29/06 , H01L21/20 , H01L27/092
Abstract: A sense amplifier (SA) includes a semiconductor substrate having a source/drain (S/D) diffusion region; a pair of SA sensing devices both disposed in the S/D diffusion region; an SA enabling device disposed in the same S/D diffusion region as where the pair of SA sensing devices are disposed in; and a sense amplifier enabling signal (SAE) line for carrying an SAE signal, for turning on the SA enabling device to discharge one of the pair of SA sensing devices during a data read from the sense amplifier, wherein the SA enabling device is arranged to provide buffer protection for source/drain terminals of the pair of SA sensing devices.
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公开(公告)号：US20190122960A1
公开(公告)日：2019-04-25
申请号：US16224159
申请日：2018-12-18
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chih-Yu Lin , Kao-Cheng Lin , Li-Wen Wang , Yen-Huei Chen
Abstract: An apparatus and method of three dimensional conductive lines comprising a first memory column segment in a first tier, a second memory column segment in a second tier, and conductive lines connecting the first memory column segment to the second memory column segment. In some embodiments a conductive line is disposed in the first tier on a first side of the memory column and in the second tier on a second side of the memory column.
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公开(公告)号：US20180269134A1
公开(公告)日：2018-09-20
申请号：US15983786
申请日：2018-05-18
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chih-Yu Lin , Kao-Cheng Lin , Li-Wen Wang , Yen-Huei Chen
CPC classification number: H01L23/481 , G11C5/063 , G11C7/18 , H01L25/0657 , H01L27/0688 , H01L27/10 , H01L2225/06541 , H01L2924/0002 , H01L2924/00
Abstract: An apparatus and method of three dimensional conductive lines comprising a first memory column segment in a first tier, a second memory column segment in a second tier, and conductive lines connecting the first memory column segment to the second memory column segment. In some embodiments a conductive line is disposed in the first tier on a first side of the memory column and in the second tier on a second side of the memory column.
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公开(公告)号：US09524920B2
公开(公告)日：2016-12-20
申请号：US14077252
申请日：2013-11-12
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chih-Yu Lin , Kao-Cheng Lin , Li-Wen Wang , Yen-Huei Chen
IPC: H01L23/48 , H01L25/065 , G11C5/06 , G11C7/18 , H01L27/06
CPC classification number: H01L23/481 , G11C5/063 , G11C7/18 , H01L25/0657 , H01L27/0688 , H01L27/10 , H01L2225/06541 , H01L2924/0002 , H01L2924/00
Abstract: An apparatus and method of three dimensional conductive lines comprising a first memory column segment in a first tier, a second memory column segment in a second tier, and conductive lines connecting the first memory column segment to the second memory column segment. In some embodiments a conductive line is disposed in the first tier on a first side of the memory column and in the second tier on a second side of the memory column.
Abstract translation: 一种三维导线的装置和方法，包括第一层中的第一存储器列段，第二层中的第二存储器列段，以及将第一存储器列段连接到第二存储器列段的导线。 在一些实施例中，导线被布置在存储器列的第一侧上的第一层中，并且位于存储器列的第二侧上的第二层中。
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