Invention Grant
- Patent Title: Reduced pin count interface
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Application No.: US16266992Application Date: 2019-02-04
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Publication No.: US10706003B2Publication Date: 2020-07-07
- Inventor: Michelle Jen , Daniel Froelich , Debendra Das Sharma , Bruce Tennant , Quinn Devine , Su Wei Lim
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Alliance IP, LLC
- Main IPC: G06F13/38
- IPC: G06F13/38 ; G06F13/42 ; G06F13/40 ; H04L29/06 ; H04L29/08

Abstract:
An apparatus is provided that includes a set of registers, and an interface of a computing block. The computing block includes one of a physical layer block or a media access control layer block. The interface includes one or more pins to transmit asynchronous signals, one or more pins to receive asynchronous signals, and a set of pins to communicate particular signals to access the set of registers, where a set of control and status signals of a defined interface are mapped to respective bits of the set of registers.
Public/Granted literature
- US20190303338A1 REDUCED PIN COUNT INTERFACE Public/Granted day:2019-10-03
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