公开(公告)号：US20160188524A1

公开(公告)日：2016-06-30

申请号：US14582734

申请日：2014-12-24

申请人： Intel Corporation

发明人： Daniel Froelich ,  David J. Harriman

IPC分类号： G06F13/42 ,  G06F13/40

CPC分类号： G06F13/4286 ,  G06F13/4059

摘要： Techniques for reducing precision timing message uncertainty are described herein. A method includes resetting an elastic buffer of a first device in response to a second device linked with the first device sending SKIP (SKP) ordered sets to the first device. The method also includes initiating a PTM handshake with the second device in response to resetting the elastic buffer. Additionally, the method includes sending PTM messages to the second device immediately after receiving the SKP ordered sets.

摘要翻译： 本文描述了用于降低精确定时消息不确定性的技术。 一种方法包括响应于与第一设备链接的第二设备，将第一设备的弹性缓冲区重置为向第一设备发送SKIP（SKP）有序集合。 该方法还包括响应于复位弹性缓冲区而启动与第二设备的PTM握手。 此外，该方法包括在接收到SKP有序集之后立即向第二设备发送PTM消息。

公开(公告)号：US20190303338A1

公开(公告)日：2019-10-03

申请号：US16266992

申请日：2019-02-04

申请人： Intel Corporation

发明人： Michelle Jen ,  Daniel Froelich ,  Debendra Das Sharma ,  Bruce Tennant ,  Quinn Devine ,  Su Wei Lim

IPC分类号： G06F13/42 ,  G06F13/40 ,  G06F13/38

摘要： An apparatus is provided that includes a set of registers, and an interface of a computing block. The computing block includes one of a physical layer block or a media access control layer block. The interface includes one or more pins to transmit asynchronous signals, one or more pins to receive asynchronous signals, and a set of pins to communicate particular signals to access the set of registers, where a set of control and status signals of a defined interface are mapped to respective bits of the set of registers.

公开(公告)号：US10706003B2

公开(公告)日：2020-07-07

申请号：US16266992

申请日：2019-02-04

申请人： Intel Corporation

发明人： Michelle Jen ,  Daniel Froelich ,  Debendra Das Sharma ,  Bruce Tennant ,  Quinn Devine ,  Su Wei Lim

IPC分类号： G06F13/38 ,  G06F13/42 ,  G06F13/40 ,  H04L29/06 ,  H04L29/08

摘要： An apparatus is provided that includes a set of registers, and an interface of a computing block. The computing block includes one of a physical layer block or a media access control layer block. The interface includes one or more pins to transmit asynchronous signals, one or more pins to receive asynchronous signals, and a set of pins to communicate particular signals to access the set of registers, where a set of control and status signals of a defined interface are mapped to respective bits of the set of registers.

公开(公告)号：US09946683B2

公开(公告)日：2018-04-17

申请号：US14582734

申请日：2014-12-24

申请人： Intel Corporation

发明人： Daniel Froelich ,  David J. Harriman

IPC分类号： G06F13/00 ,  G06F13/42 ,  G06F13/40

CPC分类号： G06F13/4286 ,  G06F13/4059

摘要： Techniques for reducing precision timing message uncertainty are described herein. A method includes resetting an elastic buffer of a first device in response to a second device linked with the first device sending SKIP (SKP) ordered sets to the first device. The method also includes initiating a PTM handshake with the second device in response to resetting the elastic buffer. Additionally, the method includes sending PTM messages to the second device immediately after receiving the SKP ordered sets.

公开(公告)号：US20170235701A1

公开(公告)日：2017-08-17

申请号：US15503097

申请日：2014-12-24

申请人： INTEL CORPORATION

发明人： Akshay Pethe ,  Mahesh Wagh ,  David Harriman ,  Su Wei Lim ,  Debendra Das Sharma ,  Daniel Froelich ,  Venkatraman Iyer ,  James Jaussi ,  Zuoguo Wu

IPC分类号： G06F13/42 ,  G06F13/38

CPC分类号： G06F13/4286 ,  G06F13/385 ,  G06F13/4027 ,  G06F2213/0042 ,  G06F2213/4002

摘要： Techniques for embedded high speed serial interface methods are described herein. The techniques include an apparatus for sideband signaling including a first serial sideband link module and a second serial sideband link module. The first serial sideband link module is to propagate packets from an upstream port to a downstream port via a first signaling lane, and the second serial sideband link module is to propagate packets from the downstream port to the upstream port via a second signaling lane.

公开(公告)号：US20160182257A1

公开(公告)日：2016-06-23

申请号：US14582105

申请日：2014-12-23

申请人： Intel Corporation

发明人： Daniel Froelich ,  Zuoguo Wu ,  Anupriya Sriramulu

IPC分类号： H04L25/02 ,  H04L25/03

CPC分类号： H04L25/0262 ,  H04L25/03057 ,  H04L25/03343 ,  H04L25/03885

摘要： An apparatus is described herein. The apparatus comprises a physical layer (PHY), wherein analog circuitry of the physical layer is to determine a data rate. The apparatus also comprises a media access layer (MAC), wherein the media access layer is to receive the data rate from the physical layer.

摘要翻译： 这里描述了一种装置。 该装置包括物理层（PHY），其中物理层的模拟电路用于确定数据速率。 该装置还包括媒体接入层（MAC），其中媒体接入层将从物理层接收数据速率。