Invention Grant
- Patent Title: Vertically stacked nFET and pFET with dual work function
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Application No.: US16564823Application Date: 2019-09-09
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Publication No.: US10748994B2Publication Date: 2020-08-18
- Inventor: Alexander Reznicek , Takashi Ando , Jingyun Zhang , Choonghyun Lee , Pouya Hashemi
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Scully, Scott, Murphy & Presser, P.C
- Agent L. Jeffrey Kelly, Esq.
- Main IPC: H01L29/06
- IPC: H01L29/06 ; H01L21/8238 ; H01L29/16 ; H01L29/423 ; H01L29/08 ; H01L29/49 ; H01L21/02 ; H01L21/306 ; H01L29/66 ; H01L21/28 ; H01L21/285 ; H01L27/12 ; H01L29/786 ; H01L21/84 ; H01L27/092 ; H01L27/06 ; H01L29/775 ; H01L21/822
Abstract:
A semiconductor structure is provided that includes a pFET device including a first functional gate structure containing at least a p-type work function metal and present on physically exposed surfaces, and between, each Si channel material nanosheet of a first set of vertically stacked and suspended Si channel material nanosheets. The structure further includes an nFET device stacked vertically above the pFET device. The nFET device includes a second functional gate structure containing at least an n-type work function metal present on physically exposed surfaces, and between, each Si channel material nanosheet of a second set of vertically stacked and suspended Si channel material nanosheets.
Public/Granted literature
- US20190393307A1 VERTICALLY STACKED NFET AND PFET WITH DUAL WORK FUNCTION Public/Granted day:2019-12-26
Information query
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