Invention Grant
- Patent Title: Multicore bus architecture with non-blocking high performance transaction credit system
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Application No.: US16430748Application Date: 2019-06-04
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Publication No.: US10795844B2Publication Date: 2020-10-06
- Inventor: David M. Thompson , Timothy D. Anderson , Joseph R. M. Zbiciak , Abhijeet A. Chachad , Kai Chirca , Matthew D. Pierson
- Applicant: TEXAS INSTRUMENTS INCORPORATED
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Brian D. Graham; Charles A. Brill; Frank D. Cimino
- Main IPC: G06F13/40
- IPC: G06F13/40 ; G06F13/42 ; H04L12/801 ; G06F13/364 ; H04L12/819

Abstract:
This invention is a bus communication protocol. A master device stores bus credits. The master device may transmit a bus transaction only if it holds sufficient number and type of bus credits. Upon transmission, the master device decrements the number of stored bus credits. The bus credits correspond to resources on a slave device for receiving bus transactions. The slave device must receive the bus transaction if accompanied by the proper credits. The slave device services the transaction. The slave device then transmits a credit return. The master device adds the corresponding number and types of credits to the stored amount. The slave device is ready to accept another bus transaction and the master device is re-enabled to initiate the bus transaction. In many types of interactions a bus agent may act as both master and slave depending upon the state of the process.
Public/Granted literature
- US20190354500A1 MULTICORE BUS ARCHITECTURE WITH NON-BLOCKING HIGH PERFORMANCE TRANSACTION CREDIT SYSTEM Public/Granted day:2019-11-21
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