Invention Grant
- Patent Title: Integrated circuit and method of manufacturing the same
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Application No.: US15954874Application Date: 2018-04-17
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Publication No.: US10833094B2Publication Date: 2020-11-10
- Inventor: Fausto Piazza , Sebastien Lagrasta , Raul Andres Bianchi , Simon Jeannot
- Applicant: STMicroelectronics (Crolles 2) SAS
- Applicant Address: FR Crolles
- Assignee: STMicroelectronics (Crolles 2) SAS
- Current Assignee: STMicroelectronics (Crolles 2) SAS
- Current Assignee Address: FR Crolles
- Agency: Crowe & Dunlevy
- Priority: com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@36d8cce
- Main IPC: H01L27/11546
- IPC: H01L27/11546 ; H01L21/28 ; H01L27/06 ; H01L49/02 ; H01L21/02 ; H01L21/3205 ; H01L21/3213 ; H01L27/11521 ; H01L29/49 ; H01L29/66 ; H01L21/8234 ; H01L27/11541

Abstract:
An integrated circuit includes a high-voltage MOS (HV) transistor and a capacitor supported by a semiconductor substrate. A gate stack of the HV transistor includes a first insulating layer over the semiconductor layer and a gate electrode formed from a first polysilicon. The capacitor includes a first electrode made of the first polysilicon and a second electrode made of a second polysilicon and at least partly resting over the first electrode. A first polysilicon layer deposited over the semiconductor substrate is patterned to form the first polysilicon of the gate electrode and first electrode, respectively. A second polysilicon layer deposited over the semiconductor substrate is patterned to form the second polysilicon of the second electrode. Silicon oxide spacers laterally border the second electrode and the gate stack of the HV transistor. Silicon nitride spacers border the silicon oxide spacers.
Public/Granted literature
- US20180233511A1 INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING THE SAME Public/Granted day:2018-08-16
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