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公开(公告)号：US10833094B2
公开(公告)日：2020-11-10
申请号：US15954874
申请日：2018-04-17
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Fausto Piazza , Sebastien Lagrasta , Raul Andres Bianchi , Simon Jeannot
IPC: H01L27/11546 , H01L21/28 , H01L27/06 , H01L49/02 , H01L21/02 , H01L21/3205 , H01L21/3213 , H01L27/11521 , H01L29/49 , H01L29/66 , H01L21/8234 , H01L27/11541
Abstract: An integrated circuit includes a high-voltage MOS (HV) transistor and a capacitor supported by a semiconductor substrate. A gate stack of the HV transistor includes a first insulating layer over the semiconductor layer and a gate electrode formed from a first polysilicon. The capacitor includes a first electrode made of the first polysilicon and a second electrode made of a second polysilicon and at least partly resting over the first electrode. A first polysilicon layer deposited over the semiconductor substrate is patterned to form the first polysilicon of the gate electrode and first electrode, respectively. A second polysilicon layer deposited over the semiconductor substrate is patterned to form the second polysilicon of the second electrode. Silicon oxide spacers laterally border the second electrode and the gate stack of the HV transistor. Silicon nitride spacers border the silicon oxide spacers.
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公开(公告)号：US20180012935A1
公开(公告)日：2018-01-11
申请号：US15694463
申请日：2017-09-01
Inventor： Philippe Boivin , Simon Jeannot
CPC classification number: H01L27/2436 , G11C13/0004 , G11C2213/79 , G11C2213/82 , H01L27/2463 , H01L45/04 , H01L45/085 , H01L45/1226 , H01L45/146 , H01L45/147 , H01L45/1666
Abstract: The disclosure relates to a memory cell formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor, the memory cell comprising a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element, the gate being formed on the active layer and having a lateral flank covered with a second insulating layer, the variable-resistance element being formed by a layer of variable-resistance material, deposited on a lateral flank of the active layer in a first trench formed through the active layer along the lateral flank of the gate, a trench conductor being formed in the first trench against a lateral flank of the layer of variable-resistance material.
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公开(公告)号：US10707270B2
公开(公告)日：2020-07-07
申请号：US16357152
申请日：2019-03-18
Inventor： Philippe Boivin , Simon Jeannot
Abstract: The disclosure relates to a memory cell formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor, the memory cell comprising a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element, the gate being formed on the active layer and having a lateral flank covered with a second insulating layer, the variable-resistance element being formed by a layer of variable-resistance material, deposited on a lateral flank of the active layer in a first trench formed through the active layer along the lateral flank of the gate, a trench conductor being formed in the first trench against a lateral flank of the layer of variable-resistance material.
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公开(公告)号：US09786755B2
公开(公告)日：2017-10-10
申请号：US14930150
申请日：2015-11-02
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Dominique Golanski , Gregory Bidal , Simon Jeannot
IPC: H01L21/84 , H01L29/423 , H01L27/12 , H01L29/06 , H01L29/08 , H01L29/66 , H01L29/78 , H01L29/788
CPC classification number: H01L29/42364 , H01L27/12 , H01L27/1207 , H01L29/0649 , H01L29/0847 , H01L29/66545 , H01L29/7838 , H01L29/7881
Abstract: An integrated circuit includes a first zone for a first transistor and a second zone for a second transistor. The transistors are supported by a substrate of the silicon-on-insulator type that includes a semiconductor film on a buried insulating layer on a carrier substrate. In the second zone, the semiconductor film has been removed. The second transistor in the second zone includes a gate-dielectric region resting on the carrier substrate that is formed by a portion of the buried insulating layer). The first transistor in the first zone includes a gate-dielectric region formed by a dielectric layer on the semiconductor film.
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公开(公告)号：US09735353B2
公开(公告)日：2017-08-15
申请号：US15098025
申请日：2016-04-13
Inventor： Philippe Boivin , Simon Jeannot
CPC classification number: H01L45/06 , G11C13/0004 , G11C2213/79 , G11C2213/82 , H01L27/2436 , H01L27/2463 , H01L45/1206 , H01L45/1226 , H01L45/1233 , H01L45/124 , H01L45/126 , H01L45/144 , H01L45/16 , H01L45/1666
Abstract: A memory cell includes a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element. The memory cell is formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor. The gate is formed on the active layer and has a lateral flank covered with a second insulating layer. The variable-resistance element includes a first layer covering a lateral flank of the active layer in a trench formed through the active layer along the lateral flank of the gate and reaching the first insulating layer, and a second layer made of a variable-resistance material.
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Patent Agency Ranking
公开(公告)号：US20160380190A1
公开(公告)日：2016-12-29
申请号：US15098025
申请日：2016-04-13
Inventor： Philippe Boivin , Simon Jeannot
IPC: H01L45/00
CPC classification number: H01L45/06 , G11C13/0004 , G11C2213/79 , G11C2213/82 , H01L27/2436 , H01L27/2463 , H01L45/1206 , H01L45/1226 , H01L45/1233 , H01L45/124 , H01L45/126 , H01L45/144 , H01L45/16 , H01L45/1666
Abstract: A memory cell includes a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element. The memory cell is formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor. The gate is formed on the active layer and has a lateral flank covered with a second insulating layer. The variable-resistance element includes a first layer covering a lateral flank of the active layer in a trench formed through the active layer along the lateral flank of the gate and reaching the first insulating layer, and a second layer made of a variable-resistance material.
Abstract translation: 存储单元包括具有控制栅极的选择晶体管和连接到可变电阻元件的第一导电端子。 存储单元形成在包括被第一绝缘层覆盖的半导体衬底的晶片中，绝缘层被由半导体制成的有源层覆盖。 栅极形成在有源层上，并具有用第二绝缘层覆盖的侧面。 可变电阻元件包括覆盖有源层的横向侧面的第一层，该沟槽沿着栅极的侧面通过有源层形成并且到达第一绝缘层的沟槽，以及由可变电阻材料制成的第二层 。
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公开(公告)号：US11957067B2
公开(公告)日：2024-04-09
申请号：US17328917
申请日：2021-05-24
Inventor： Philippe Boivin , Simon Jeannot
CPC classification number: H10N70/231 , H10B63/30 , H10B63/80 , H10N70/011 , H10N70/061 , H10N70/253 , H10N70/823 , H10N70/826 , H10N70/8265 , H10N70/8413 , H10N70/8828 , G11C13/0004 , G11C2213/79 , G11C2213/82
Abstract: A memory cell includes a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element. The memory cell is formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor. The gate is formed on the active layer and has a lateral flank covered with a second insulating layer. The variable-resistance element includes a first layer covering a lateral flank of the active layer in a trench formed through the active layer along the lateral flank of the gate and reaching the first insulating layer, and a second layer made of a variable-resistance material.
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公开(公告)号：US20170317275A1
公开(公告)日：2017-11-02
申请号：US15654405
申请日：2017-07-19
Inventor： Philippe Boivin , Simon Jeannot
CPC classification number: H01L45/06 , G11C13/0004 , G11C2213/79 , G11C2213/82 , H01L27/2436 , H01L27/2463 , H01L45/1206 , H01L45/1226 , H01L45/1233 , H01L45/124 , H01L45/126 , H01L45/144 , H01L45/16 , H01L45/1666
Abstract: A memory cell includes a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element. The memory cell is formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor. The gate is formed on the active layer and has a lateral flank covered with a second insulating layer. The variable-resistance element includes a first layer covering a lateral flank of the active layer in a trench formed through the active layer along the lateral flank of the gate and reaching the first insulating layer, and a second layer made of a variable-resistance material.
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公开(公告)号：US09793321B2
公开(公告)日：2017-10-17
申请号：US14970347
申请日：2015-12-15
Inventor： Philippe Boivin , Simon Jeannot
CPC classification number: H01L27/2436 , G11C13/0004 , G11C2213/79 , G11C2213/82 , H01L27/2463 , H01L45/04 , H01L45/085 , H01L45/1226 , H01L45/146 , H01L45/147 , H01L45/1666
Abstract: The disclosure relates to a memory cell formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor, the memory cell comprising a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element, the gate being formed on the active layer and having a lateral flank covered with a second insulating layer, the variable-resistance element being formed by a layer of variable-resistance material, deposited on a lateral flank of the active layer in a first trench formed through the active layer along the lateral flank of the gate, a trench conductor being formed in the first trench against a lateral flank of the layer of variable-resistance material.
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公开(公告)号：US11031550B2
公开(公告)日：2021-06-08
申请号：US16457855
申请日：2019-06-28
Inventor： Philippe Boivin , Simon Jeannot
Abstract: A memory cell includes a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element. The memory cell is formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor. The gate is formed on the active layer and has a lateral flank covered with a second insulating layer. The variable-resistance element includes a first layer covering a lateral flank of the active layer in a trench formed through the active layer along the lateral flank of the gate and reaching the first insulating layer, and a second layer made of a variable-resistance material.
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