公开(公告)号：US20170186759A1

公开(公告)日：2017-06-29

申请号：US15133394

申请日：2016-04-20

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Fausto Piazza ,  Sebastien Lagrasta ,  Raul Andres Bianchi ,  Simon Jeannot

IPC: H01L27/115 ,  H01L21/3213 ,  H01L29/49 ,  H01L21/3205 ,  H01L21/02 ,  H01L29/66 ,  H01L21/28 ,  H01L49/02

CPC classification number: H01L27/11546 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/28035 ,  H01L21/28273 ,  H01L21/32055 ,  H01L21/32133 ,  H01L21/823468 ,  H01L27/0629 ,  H01L27/11521 ,  H01L27/11541 ,  H01L28/00 ,  H01L28/60 ,  H01L29/4916 ,  H01L29/6656 ,  H01L29/66825

Abstract: An integrated circuit includes a high-voltage MOS (HV) transistor and a capacitor supported by a semiconductor substrate. A gate stack of the HV transistor includes a first insulating layer over the semiconductor layer and a gate electrode formed from a first polysilicon. The capacitor includes a first electrode made of the first polysilicon and a second electrode made of a second polysilicon and at least partly resting over the first electrode. A first polysilicon layer deposited over the semiconductor substrate is patterned to form the first polysilicon of the gate electrode and first electrode, respectively. A second polysilicon layer deposited over the semiconductor substrate is patterned to form the second polysilicon of the second electrode. Silicon oxide spacers laterally border the second electrode and the gate stack of the HV transistor. Silicon nitride spacers border the silicon oxide spacers.

公开(公告)号：US10833094B2

公开(公告)日：2020-11-10

申请号：US15954874

申请日：2018-04-17

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Fausto Piazza ,  Sebastien Lagrasta ,  Raul Andres Bianchi ,  Simon Jeannot

IPC: H01L27/11546 ,  H01L21/28 ,  H01L27/06 ,  H01L49/02 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/3213 ,  H01L27/11521 ,  H01L29/49 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/11541

Abstract: An integrated circuit includes a high-voltage MOS (HV) transistor and a capacitor supported by a semiconductor substrate. A gate stack of the HV transistor includes a first insulating layer over the semiconductor layer and a gate electrode formed from a first polysilicon. The capacitor includes a first electrode made of the first polysilicon and a second electrode made of a second polysilicon and at least partly resting over the first electrode. A first polysilicon layer deposited over the semiconductor substrate is patterned to form the first polysilicon of the gate electrode and first electrode, respectively. A second polysilicon layer deposited over the semiconductor substrate is patterned to form the second polysilicon of the second electrode. Silicon oxide spacers laterally border the second electrode and the gate stack of the HV transistor. Silicon nitride spacers border the silicon oxide spacers.

公开(公告)号：US11495609B2

公开(公告)日：2022-11-08

申请号：US17092551

申请日：2020-11-09

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Fausto Piazza ,  Sebastien Lagrasta ,  Raul Andres Bianchi ,  Simon Jeannot

IPC: H01L27/11546 ,  H01L21/28 ,  H01L27/06 ,  H01L49/02 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/3213 ,  H01L27/11521 ,  H01L29/49 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/11541

Abstract: An integrated circuit includes a high-voltage MOS (HV) transistor and a capacitor supported by a semiconductor substrate. A gate stack of the HV transistor includes a first insulating layer over the semiconductor layer and a gate electrode formed from a first polysilicon. The capacitor includes a first electrode made of the first polysilicon and a second electrode made of a second polysilicon and at least partly resting over the first electrode. A first polysilicon layer deposited over the semiconductor substrate is patterned to form the first polysilicon of the gate electrode and first electrode, respectively. A second polysilicon layer deposited over the semiconductor substrate is patterned to form the second polysilicon of the second electrode. Silicon oxide spacers laterally border the second electrode and the gate stack of the HV transistor. Silicon nitride spacers border the silicon oxide spacers.

公开(公告)号：US09978764B2

公开(公告)日：2018-05-22

申请号：US15133394

申请日：2016-04-20

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Fausto Piazza ,  Sebastien Lagrasta ,  Raul Andres Bianchi ,  Simon Jeannot

IPC: H01L27/115 ,  H01L27/11546 ,  H01L21/02 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/3213 ,  H01L27/11521 ,  H01L49/02 ,  H01L29/49 ,  H01L29/66 ,  H01L27/06 ,  H01L21/8234 ,  H01L27/11541

CPC classification number: H01L27/11546 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/28035 ,  H01L21/28273 ,  H01L21/32055 ,  H01L21/32133 ,  H01L21/823468 ,  H01L27/0629 ,  H01L27/11521 ,  H01L27/11541 ,  H01L28/00 ,  H01L28/60 ,  H01L29/4916 ,  H01L29/6656 ,  H01L29/66825

Abstract: An integrated circuit includes a high-voltage MOS (HV) transistor and a capacitor supported by a semiconductor substrate. A gate stack of the HV transistor includes a first insulating layer over the semiconductor layer and a gate electrode formed from a first polysilicon. The capacitor includes a first electrode made of the first polysilicon and a second electrode made of a second polysilicon and at least partly resting over the first electrode. A first polysilicon layer deposited over the semiconductor substrate is patterned to form the first polysilicon of the gate electrode and first electrode, respectively. A second polysilicon layer deposited over the semiconductor substrate is patterned to form the second polysilicon of the second electrode. Silicon oxide spacers laterally border the second electrode and the gate stack of the HV transistor. Silicon nitride spacers border the silicon oxide spacers.