Invention Grant
- Patent Title: Forming gate line-end of semiconductor structures
-
Application No.: US15922682Application Date: 2018-03-15
-
Publication No.: US10943822B2Publication Date: 2021-03-09
- Inventor: Che-Liang Chung , Che-Hao Tu , Kei-Wei Chen , Chih-Wen Liu , You-Shiang Lin , Yi-Ching Liang
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Seed IP Law Group LLP
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L21/3213 ; H01L23/532 ; H01L29/78 ; H01L23/535
Abstract:
The current disclosure provides a semiconductor fabrication method that defines the height of gate structures at the formation of the gate structure. A gate line-end region is formed by removing a portion of a gate structure. A resulted recess is filled with a dielectric material is chosen to have a material property suitable for a later contact formation process of forming a metal contact. A metal contact structure is formed through the recess filling dielectric layer to connect to a gate structure and/or a source/drain region.
Public/Granted literature
- US20190287852A1 FORMING GATE LINE-END OF SEMICONDUCTOR STRUCTURES Public/Granted day:2019-09-19
Information query
IPC分类:
