公开(公告)号：US20210166972A1

公开(公告)日：2021-06-03

申请号：US17172003

申请日：2021-02-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Liang CHUNG ,  Che-Hao Tu ,  KEI-WEI CHEN ,  Chih-Wen Liu ,  You-Shiang Lin ,  Yi-Ching Liang

IPC: H01L21/768 ,  H01L29/78 ,  H01L23/535 ,  H01L21/3213 ,  H01L23/532

Abstract: The current disclosure provides a semiconductor fabrication method that defines the height of gate structures at the formation of the gate structure. A gate line-end region is formed by removing a portion of a gate structure. A resulted recess is filled with a dielectric material is chosen to have a material property suitable for a later contact formation process of forming a metal contact. A metal contact structure is formed through the recess filling dielectric layer to connect to a gate structure and/or a source/drain region.

公开(公告)号：US12068196B2

公开(公告)日：2024-08-20

申请号：US17172003

申请日：2021-02-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Liang Chung ,  Che-Hao Tu ,  Kei-Wei Chen ,  Chih-Wen Liu ,  You-Shiang Lin ,  Yi-Ching Liang

IPC: H01L21/768 ,  H01L21/3213 ,  H01L23/532 ,  H01L23/535 ,  H01L29/78

CPC classification number: H01L21/76895 ,  H01L21/32139 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76879 ,  H01L23/53295 ,  H01L23/535 ,  H01L29/78

Abstract: The current disclosure provides a semiconductor fabrication method that defines the height of gate structures at the formation of the gate structure. A gate line-end region is formed by removing a portion of a gate structure. A resulted recess is filled with a dielectric material is chosen to have a material property suitable for a later contact formation process of forming a metal contact. A metal contact structure is formed through the recess filling dielectric layer to connect to a gate structure and/or a source/drain region.

公开(公告)号：US10943822B2

公开(公告)日：2021-03-09

申请号：US15922682

申请日：2018-03-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Liang Chung ,  Che-Hao Tu ,  Kei-Wei Chen ,  Chih-Wen Liu ,  You-Shiang Lin ,  Yi-Ching Liang

IPC: H01L21/768 ,  H01L21/3213 ,  H01L23/532 ,  H01L29/78 ,  H01L23/535

Abstract: The current disclosure provides a semiconductor fabrication method that defines the height of gate structures at the formation of the gate structure. A gate line-end region is formed by removing a portion of a gate structure. A resulted recess is filled with a dielectric material is chosen to have a material property suitable for a later contact formation process of forming a metal contact. A metal contact structure is formed through the recess filling dielectric layer to connect to a gate structure and/or a source/drain region.

公开(公告)号：US20190287852A1

公开(公告)日：2019-09-19

申请号：US15922682

申请日：2018-03-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Liang Chung ,  Che-Hao Tu ,  KEI-WEI CHEN ,  Chih-Wen Liu ,  You-Shiang Lin ,  Yi-Ching Liang

IPC: H01L21/768 ,  H01L29/78 ,  H01L23/535 ,  H01L23/532 ,  H01L21/3213

Abstract: The current disclosure provides a semiconductor fabrication method that defines the height of gate structures at the formation of the gate structure. A gate line-end region is formed by removing a portion of a gate structure. A resulted recess is filled with a dielectric material is chosen to have a material property suitable for a later contact formation process of forming a metal contact. A metal contact structure is formed through the recess filling dielectric layer to connect to a gate structure and/or a source/drain region.