公开(公告)号：US20210166972A1

公开(公告)日：2021-06-03

申请号：US17172003

申请日：2021-02-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Liang CHUNG ,  Che-Hao Tu ,  KEI-WEI CHEN ,  Chih-Wen Liu ,  You-Shiang Lin ,  Yi-Ching Liang

IPC: H01L21/768 ,  H01L29/78 ,  H01L23/535 ,  H01L21/3213 ,  H01L23/532

Abstract: The current disclosure provides a semiconductor fabrication method that defines the height of gate structures at the formation of the gate structure. A gate line-end region is formed by removing a portion of a gate structure. A resulted recess is filled with a dielectric material is chosen to have a material property suitable for a later contact formation process of forming a metal contact. A metal contact structure is formed through the recess filling dielectric layer to connect to a gate structure and/or a source/drain region.

公开(公告)号：US20170256414A1

公开(公告)日：2017-09-07

申请号：US15058956

申请日：2016-03-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wen Liu ,  Che-Hao Tu ,  Po-Chin Nien ,  William Weilun Hong ,  Ying-Tsung Chen

IPC: H01L21/306 ,  H01L23/544 ,  H01L21/67 ,  H01L21/66

CPC classification number: H01L21/30625 ,  B24B37/30 ,  H01L21/32115 ,  H01L21/3212 ,  H01L21/67092 ,  H01L22/12 ,  H01L22/26 ,  H01L23/544 ,  H01L2223/54493

Abstract: A method includes measuring a topography of a wafer, determining that a first portion of the wafer has a greater thickness than a specified thickness. The method further includes, after measuring the wafer, performing a Chemical Mechanical Polishing (CMP) process to a first side of the wafer, and during application of the CMP process, applying additional pressure to a region of the wafer, the region comprising an asymmetric part of the wafer, the region including at least a part of the first portion of the wafer.

公开(公告)号：US09595450B2

公开(公告)日：2017-03-14

申请号：US14141028

申请日：2013-12-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Hao Tu ,  William Weilun Hong ,  Ying-Tsung Chen

IPC: H01L27/088 ,  H01L21/3105 ,  H01L27/092 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L21/31055 ,  H01L21/31053 ,  H01L21/76224 ,  H01L21/823462 ,  H01L21/823481 ,  H01L21/823878 ,  H01L27/088 ,  H01L27/092 ,  H01L27/0928 ,  H01L29/66545

Abstract: A method of forming an integrated circuit device includes forming dummy gates over a semiconductor substrate, depositing a first dielectric layer over the dummy gates, chemical mechanical polishing to recede the first dielectric layer to the height of the dummy gates, etching to recess the first dielectric layer below the height of the gates, depositing one or more additional dielectric layers over the first dielectric layer, and chemical mechanical polishing to recede the one or more additional dielectric layers to the height of the gates. The method provides integrated circuit devices having metal gate electrodes and an inter-level dielectric at the gate level that includes a capping layer. The capping layer resists etching and preserves the gate height through a replacement gate process.

Abstract translation: 形成集成电路器件的方法包括在半导体衬底上形成伪栅极，在虚拟栅极上沉积第一介电层，化学机械抛光以将第一介电层退回到虚拟栅极的高度，蚀刻以使第一电介质 在栅极的高度以下，在第一介电层上沉积一个或多个附加电介质层，以及化学机械抛光以将一个或多个另外的介电层退回到栅极的高度。 该方法提供了集成电路器件，其具有金属栅极电极和栅极电平处的包括封盖层的级间电介质。 封盖层抵抗蚀刻并通过替换浇口工艺保持浇口高度。

公开(公告)号：US12068196B2

公开(公告)日：2024-08-20

申请号：US17172003

申请日：2021-02-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Liang Chung ,  Che-Hao Tu ,  Kei-Wei Chen ,  Chih-Wen Liu ,  You-Shiang Lin ,  Yi-Ching Liang

IPC: H01L21/768 ,  H01L21/3213 ,  H01L23/532 ,  H01L23/535 ,  H01L29/78

CPC classification number: H01L21/76895 ,  H01L21/32139 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76879 ,  H01L23/53295 ,  H01L23/535 ,  H01L29/78

Abstract: The current disclosure provides a semiconductor fabrication method that defines the height of gate structures at the formation of the gate structure. A gate line-end region is formed by removing a portion of a gate structure. A resulted recess is filled with a dielectric material is chosen to have a material property suitable for a later contact formation process of forming a metal contact. A metal contact structure is formed through the recess filling dielectric layer to connect to a gate structure and/or a source/drain region.

公开(公告)号：US11951587B2

公开(公告)日：2024-04-09

申请号：US16538464

申请日：2019-08-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Liang Chung ,  Che-Hao Tu ,  Kei-Wei Chen ,  Chih-Wen Liu

IPC: B24B37/005 ,  B24B51/00 ,  H01L21/67

CPC classification number: B24B37/005 ,  B24B51/00 ,  H01L21/67253

Abstract: The present disclosure is directed to techniques of zone-based target control in chemical mechanical polishing of wafers. Multiple zones are identified on a surface of a wafer. The CMP target is achieved on each zone in a sequence of CMP processes. Each CMP process in the sequence achieves the CMP target for only one zone, using a CMP process selective to other zones.

公开(公告)号：US20210225657A1

公开(公告)日：2021-07-22

申请号：US17220595

申请日：2021-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Hao Tu ,  William Weilun Hong ,  Ying-Tsung Chen

IPC: H01L21/3105 ,  H01L21/306 ,  H01L21/8234

Abstract: A method of removing a hard mask is provided. Gate stacks are patterned on a substrate, where the gate stacks include a polysilicon layer and the hard mask deposited over the polysilicon layer. A dielectric layer is deposited on the substrate and on the patterned gate stacks. A first portion of the dielectric layer is planarized by chemical mechanical polishing (CMP) to remove a topography of the dielectric layer. The hard mask and a second portion of the dielectric layer are removed by the CMP.

公开(公告)号：US20240105460A1

公开(公告)日：2024-03-28

申请号：US18524896

申请日：2023-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Hao Tu ,  William Weilun Hong ,  Ying-Tsung Chen

IPC: H01L21/3105 ,  H01L21/306 ,  H01L21/8234

CPC classification number: H01L21/31053 ,  H01L21/30625 ,  H01L21/823437 ,  H01L21/823456 ,  H01L21/32139

Abstract: A method of removing a hard mask is provided. Gate stacks are patterned on a substrate, where the gate stacks include a polysilicon layer and the hard mask deposited over the polysilicon layer. A dielectric layer is deposited on the substrate and on the patterned gate stacks. A first portion of the dielectric layer is planarized by chemical mechanical polishing (CMP) to remove a topography of the dielectric layer. The hard mask and a second portion of the dielectric layer are removed by the CMP.

公开(公告)号：US11854821B2

公开(公告)日：2023-12-26

申请号：US17220595

申请日：2021-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Hao Tu ,  William Weilun Hong ,  Ying-Tsung Chen

IPC: H01L21/3105 ,  H01L21/306 ,  H01L21/8234 ,  H01L21/3213 ,  H01L21/28

CPC classification number: H01L21/31053 ,  H01L21/30625 ,  H01L21/823437 ,  H01L21/823456 ,  H01L21/28123 ,  H01L21/32139

Abstract: A method of removing a hard mask is provided. Gate stacks are patterned on a substrate, where the gate stacks include a polysilicon layer and the hard mask deposited over the polysilicon layer. A dielectric layer is deposited on the substrate and on the patterned gate stacks. A first portion of the dielectric layer is planarized by chemical mechanical polishing (CMP) to remove a topography of the dielectric layer. The hard mask and a second portion of the dielectric layer are removed by the CMP.

公开(公告)号：US09922837B2

公开(公告)日：2018-03-20

申请号：US15058956

申请日：2016-03-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wen Liu ,  Che-Hao Tu ,  Po-Chin Nien ,  William Weilun Hong ,  Ying-Tsung Chen

IPC: H01L21/302 ,  H01L21/306 ,  H01L21/66 ,  H01L23/544 ,  H01L21/67 ,  H01L21/321

CPC classification number: H01L21/30625 ,  B24B37/30 ,  H01L21/32115 ,  H01L21/3212 ,  H01L21/67092 ,  H01L22/12 ,  H01L22/26 ,  H01L23/544 ,  H01L2223/54493

Abstract: A method includes measuring a topography of a wafer, determining that a first portion of the wafer has a greater thickness than a specified thickness. The method further includes, after measuring the wafer, performing a Chemical Mechanical Polishing (CMP) process to a first side of the wafer, and during application of the CMP process, applying additional pressure to a region of the wafer, the region comprising an asymmetric part of the wafer, the region including at least a part of the first portion of the wafer.

公开(公告)号：US10943822B2

公开(公告)日：2021-03-09

申请号：US15922682

申请日：2018-03-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Liang Chung ,  Che-Hao Tu ,  Kei-Wei Chen ,  Chih-Wen Liu ,  You-Shiang Lin ,  Yi-Ching Liang

IPC: H01L21/768 ,  H01L21/3213 ,  H01L23/532 ,  H01L29/78 ,  H01L23/535

Abstract: The current disclosure provides a semiconductor fabrication method that defines the height of gate structures at the formation of the gate structure. A gate line-end region is formed by removing a portion of a gate structure. A resulted recess is filled with a dielectric material is chosen to have a material property suitable for a later contact formation process of forming a metal contact. A metal contact structure is formed through the recess filling dielectric layer to connect to a gate structure and/or a source/drain region.