公开(公告)号：US10160088B2

公开(公告)日：2018-12-25

申请号：US15797779

申请日：2017-10-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Liang Chung ,  Chun-Kai Tai ,  Shich-Chang Suen ,  Wei-Chen Hsiao

IPC: B24B53/017 ,  B24B37/005 ,  B24B37/26 ,  B24B49/12

Abstract: A method for polishing a polishing pad includes detecting a presence of a defect formed on a groove of a polishing pad; removing the defect from the groove of the polishing pad; after removing the defect, measuring a remaining depth of the groove; and based on the measured remaining depth of the groove, applying a polishing condition on the groove.

公开(公告)号：US12068196B2

公开(公告)日：2024-08-20

申请号：US17172003

申请日：2021-02-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Liang Chung ,  Che-Hao Tu ,  Kei-Wei Chen ,  Chih-Wen Liu ,  You-Shiang Lin ,  Yi-Ching Liang

IPC: H01L21/768 ,  H01L21/3213 ,  H01L23/532 ,  H01L23/535 ,  H01L29/78

CPC classification number: H01L21/76895 ,  H01L21/32139 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76879 ,  H01L23/53295 ,  H01L23/535 ,  H01L29/78

Abstract: The current disclosure provides a semiconductor fabrication method that defines the height of gate structures at the formation of the gate structure. A gate line-end region is formed by removing a portion of a gate structure. A resulted recess is filled with a dielectric material is chosen to have a material property suitable for a later contact formation process of forming a metal contact. A metal contact structure is formed through the recess filling dielectric layer to connect to a gate structure and/or a source/drain region.

公开(公告)号：US11951587B2

公开(公告)日：2024-04-09

申请号：US16538464

申请日：2019-08-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Liang Chung ,  Che-Hao Tu ,  Kei-Wei Chen ,  Chih-Wen Liu

IPC: B24B37/005 ,  B24B51/00 ,  H01L21/67

CPC classification number: B24B37/005 ,  B24B51/00 ,  H01L21/67253

Abstract: The present disclosure is directed to techniques of zone-based target control in chemical mechanical polishing of wafers. Multiple zones are identified on a surface of a wafer. The CMP target is achieved on each zone in a sequence of CMP processes. Each CMP process in the sequence achieves the CMP target for only one zone, using a CMP process selective to other zones.

公开(公告)号：US20180043495A1

公开(公告)日：2018-02-15

申请号：US15797779

申请日：2017-10-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Liang Chung ,  Chun-Kai Tai ,  Shich-Chang Suen ,  Wei-Chen Hsiao

IPC: B24B37/005 ,  B24B37/26

CPC classification number: B24B37/005 ,  B24B37/26 ,  B24B49/12 ,  B24B53/017

Abstract: A method for polishing a polishing pad includes detecting a presence of a defect formed on a groove of a polishing pad; removing the defect from the groove of the polishing pad; after removing the defect, measuring a remaining depth of the groove; and based on the measured remaining depth of the groove, applying a polishing condition on the groove.

公开(公告)号：US10943822B2

公开(公告)日：2021-03-09

申请号：US15922682

申请日：2018-03-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Liang Chung ,  Che-Hao Tu ,  Kei-Wei Chen ,  Chih-Wen Liu ,  You-Shiang Lin ,  Yi-Ching Liang

IPC: H01L21/768 ,  H01L21/3213 ,  H01L23/532 ,  H01L29/78 ,  H01L23/535

Abstract: The current disclosure provides a semiconductor fabrication method that defines the height of gate structures at the formation of the gate structure. A gate line-end region is formed by removing a portion of a gate structure. A resulted recess is filled with a dielectric material is chosen to have a material property suitable for a later contact formation process of forming a metal contact. A metal contact structure is formed through the recess filling dielectric layer to connect to a gate structure and/or a source/drain region.

公开(公告)号：US20200094369A1

公开(公告)日：2020-03-26

申请号：US16538464

申请日：2019-08-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Liang Chung ,  Che-Hao Tu ,  Kei-Wei Chen ,  Chih-Wen Liu

IPC: B24B37/005 ,  B24B51/00 ,  H01L21/67

Abstract: The present disclosure is directed to techniques of zone-based target control in chemical mechanical polishing of wafers. Multiple zones are identified on a surface of a wafer. The CMP target is achieved on each zone in a sequence of CMP processes. Each CMP process in the sequence achieves the CMP target for only one zone, using a CMP process selective to other zones.

公开(公告)号：US20190287852A1

公开(公告)日：2019-09-19

申请号：US15922682

申请日：2018-03-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Liang Chung ,  Che-Hao Tu ,  KEI-WEI CHEN ,  Chih-Wen Liu ,  You-Shiang Lin ,  Yi-Ching Liang

IPC: H01L21/768 ,  H01L29/78 ,  H01L23/535 ,  H01L23/532 ,  H01L21/3213

Abstract: The current disclosure provides a semiconductor fabrication method that defines the height of gate structures at the formation of the gate structure. A gate line-end region is formed by removing a portion of a gate structure. A resulted recess is filled with a dielectric material is chosen to have a material property suitable for a later contact formation process of forming a metal contact. A metal contact structure is formed through the recess filling dielectric layer to connect to a gate structure and/or a source/drain region.