公开(公告)号：US20210166972A1

公开(公告)日：2021-06-03

申请号：US17172003

申请日：2021-02-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Liang CHUNG ,  Che-Hao Tu ,  KEI-WEI CHEN ,  Chih-Wen Liu ,  You-Shiang Lin ,  Yi-Ching Liang

IPC: H01L21/768 ,  H01L29/78 ,  H01L23/535 ,  H01L21/3213 ,  H01L23/532

Abstract: The current disclosure provides a semiconductor fabrication method that defines the height of gate structures at the formation of the gate structure. A gate line-end region is formed by removing a portion of a gate structure. A resulted recess is filled with a dielectric material is chosen to have a material property suitable for a later contact formation process of forming a metal contact. A metal contact structure is formed through the recess filling dielectric layer to connect to a gate structure and/or a source/drain region.

公开(公告)号：US20170256414A1

公开(公告)日：2017-09-07

申请号：US15058956

申请日：2016-03-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wen Liu ,  Che-Hao Tu ,  Po-Chin Nien ,  William Weilun Hong ,  Ying-Tsung Chen

IPC: H01L21/306 ,  H01L23/544 ,  H01L21/67 ,  H01L21/66

CPC classification number: H01L21/30625 ,  B24B37/30 ,  H01L21/32115 ,  H01L21/3212 ,  H01L21/67092 ,  H01L22/12 ,  H01L22/26 ,  H01L23/544 ,  H01L2223/54493

Abstract: A method includes measuring a topography of a wafer, determining that a first portion of the wafer has a greater thickness than a specified thickness. The method further includes, after measuring the wafer, performing a Chemical Mechanical Polishing (CMP) process to a first side of the wafer, and during application of the CMP process, applying additional pressure to a region of the wafer, the region comprising an asymmetric part of the wafer, the region including at least a part of the first portion of the wafer.

公开(公告)号：US10943822B2

公开(公告)日：2021-03-09

申请号：US15922682

申请日：2018-03-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Liang Chung ,  Che-Hao Tu ,  Kei-Wei Chen ,  Chih-Wen Liu ,  You-Shiang Lin ,  Yi-Ching Liang

IPC: H01L21/768 ,  H01L21/3213 ,  H01L23/532 ,  H01L29/78 ,  H01L23/535

Abstract: The current disclosure provides a semiconductor fabrication method that defines the height of gate structures at the formation of the gate structure. A gate line-end region is formed by removing a portion of a gate structure. A resulted recess is filled with a dielectric material is chosen to have a material property suitable for a later contact formation process of forming a metal contact. A metal contact structure is formed through the recess filling dielectric layer to connect to a gate structure and/or a source/drain region.

公开(公告)号：US20210023678A1

公开(公告)日：2021-01-28

申请号：US17068375

申请日：2020-10-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wen Liu ,  Hao-Yun Cheng ,  Che-Hao Tu ,  Kei-Wei Chen

IPC: B24B57/02 ,  B24B37/10 ,  H01L21/306 ,  B24B37/04 ,  B24B37/30

Abstract: A system controls a flow of a chemical mechanical polish (CMP) slurry into a chamber to form a slurry reservoir within the chamber. Once the slurry reservoir has been formed within the chamber, the system moves a polishing head to position and force a surface of a wafer that is attached to the polishing head into contact with a polishing pad attached to a platen within the chamber. A wafer/pad interface is formed at the surface of the wafer forced into contact with the polishing pad and the wafer/pad interface is disposed below an upper surface of the slurry reservoir. During CMP processing, the system controls one or more of a level, a force, and a rotation of the platen, a position, a force and a rotation of the polishing head to conduct the CMP processing of the surface of the wafer at the wafer/pad interface.

公开(公告)号：US20200094369A1

公开(公告)日：2020-03-26

申请号：US16538464

申请日：2019-08-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Liang Chung ,  Che-Hao Tu ,  Kei-Wei Chen ,  Chih-Wen Liu

IPC: B24B37/005 ,  B24B51/00 ,  H01L21/67

Abstract: The present disclosure is directed to techniques of zone-based target control in chemical mechanical polishing of wafers. Multiple zones are identified on a surface of a wafer. The CMP target is achieved on each zone in a sequence of CMP processes. Each CMP process in the sequence achieves the CMP target for only one zone, using a CMP process selective to other zones.

公开(公告)号：US20190287852A1

公开(公告)日：2019-09-19

申请号：US15922682

申请日：2018-03-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Liang Chung ,  Che-Hao Tu ,  KEI-WEI CHEN ,  Chih-Wen Liu ,  You-Shiang Lin ,  Yi-Ching Liang

IPC: H01L21/768 ,  H01L29/78 ,  H01L23/535 ,  H01L23/532 ,  H01L21/3213

Abstract: The current disclosure provides a semiconductor fabrication method that defines the height of gate structures at the formation of the gate structure. A gate line-end region is formed by removing a portion of a gate structure. A resulted recess is filled with a dielectric material is chosen to have a material property suitable for a later contact formation process of forming a metal contact. A metal contact structure is formed through the recess filling dielectric layer to connect to a gate structure and/or a source/drain region.

公开(公告)号：US09922837B2

公开(公告)日：2018-03-20

申请号：US15058956

申请日：2016-03-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wen Liu ,  Che-Hao Tu ,  Po-Chin Nien ,  William Weilun Hong ,  Ying-Tsung Chen

IPC: H01L21/302 ,  H01L21/306 ,  H01L21/66 ,  H01L23/544 ,  H01L21/67 ,  H01L21/321

CPC classification number: H01L21/30625 ,  B24B37/30 ,  H01L21/32115 ,  H01L21/3212 ,  H01L21/67092 ,  H01L22/12 ,  H01L22/26 ,  H01L23/544 ,  H01L2223/54493

Abstract: A method includes measuring a topography of a wafer, determining that a first portion of the wafer has a greater thickness than a specified thickness. The method further includes, after measuring the wafer, performing a Chemical Mechanical Polishing (CMP) process to a first side of the wafer, and during application of the CMP process, applying additional pressure to a region of the wafer, the region comprising an asymmetric part of the wafer, the region including at least a part of the first portion of the wafer.

公开(公告)号：US12068196B2

公开(公告)日：2024-08-20

申请号：US17172003

申请日：2021-02-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Liang Chung ,  Che-Hao Tu ,  Kei-Wei Chen ,  Chih-Wen Liu ,  You-Shiang Lin ,  Yi-Ching Liang

IPC: H01L21/768 ,  H01L21/3213 ,  H01L23/532 ,  H01L23/535 ,  H01L29/78

CPC classification number: H01L21/76895 ,  H01L21/32139 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76879 ,  H01L23/53295 ,  H01L23/535 ,  H01L29/78

Abstract: The current disclosure provides a semiconductor fabrication method that defines the height of gate structures at the formation of the gate structure. A gate line-end region is formed by removing a portion of a gate structure. A resulted recess is filled with a dielectric material is chosen to have a material property suitable for a later contact formation process of forming a metal contact. A metal contact structure is formed through the recess filling dielectric layer to connect to a gate structure and/or a source/drain region.

公开(公告)号：US11951587B2

公开(公告)日：2024-04-09

申请号：US16538464

申请日：2019-08-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Liang Chung ,  Che-Hao Tu ,  Kei-Wei Chen ,  Chih-Wen Liu

IPC: B24B37/005 ,  B24B51/00 ,  H01L21/67

CPC classification number: B24B37/005 ,  B24B51/00 ,  H01L21/67253

Abstract: The present disclosure is directed to techniques of zone-based target control in chemical mechanical polishing of wafers. Multiple zones are identified on a surface of a wafer. The CMP target is achieved on each zone in a sequence of CMP processes. Each CMP process in the sequence achieves the CMP target for only one zone, using a CMP process selective to other zones.